GHz Clock Frequency Research Articles

Foundry fabricated compact slow-light Mach-Zehnder modulator and photodetector for on-chip analog photonic computing

This work presents a scaling pathway of on-chip analog photonic computing using foundry-fabricated silicon electro-optic (EO) slow-light Mach-Zehnder modulators (SL-MZMs) and compact Ge photodetectors (PDs) to construct a computing unit. Two SL-MZMs with phase shifter (PS) lengths of 500 μm and 150 μm are studied in this work. The bit resolution, nonlinearity, clock frequency, and power consumption of the photonic computing link, including an RF amplifier, on-chip SL-MZM, and a PD, are thoroughly investigated. The computing link using the SL-MZM with 500 μm has demonstrated a low normalized mean square error (NMSE) of 0.0305 at 8-bit resolution under 3.2 GHz clock frequency. Under the setting of 6-bit resolution at a clock frequency of 800 MHz, high computing accuracy was achieved with a measured NMSE of 0.0018 using the SL-MZM with 150 μm PS length. Using the Google Speed Commands dataset to run a voice keyword spotting task, we determine that 6-bit resolution operating at 3.2 GHz achieves the optimal power-accuracy trade-off. We show a 20× improvement in energy efficiency and a 3.35× improvement in area efficiency compared to NVIDIA V100 GPU [“Volta: Performance and programmability,” IEEE Micro 38(2), 42 (2018)10.1109/MM.2018.022071134 ]. These results show that our compact SL-MZMs and PDs promise to scale up photonic computing for practical machine-learning applications.

Charge pump-based PVT-resilient 45 nm CMOS dynamic comparator leveraging high speed and power efficiency

High-speed, low-power consumption, compact area, and high resolution are critical for analog /mixed signal applications. This article presents a novel design for a dynamic latch comparator that achieves exceptional speed, minimal power consumption, and a significantly reduced die area. The innovative comparator leverages a novel charge shared logic-based reset technique, which enables unparalleled speed and power efficiency. Rigorous simulations and analyses confirm that the delay time is drastically reduced compared to traditional dynamic latched comparators. The results clearly indicate that the proposed design exhibits high tolerance to PVT (process, voltage, and temperature) variations, making it highly suitable for mixed-signal applications. Designed and simulated using advanced 45 nm CMOS technology, the proposed circuit achieves an impressive delay of 18.5 ps and a remarkably low power consumption of 3.66 μW at a 1 V supply voltage and 1 GHz clock frequency.

The impact of spot‐size on single‐photon avalanche diode timing‐jitter and quantum key distribution

AbstractIn free‐space implementations of Quantum key distribution (QKD), the wide adoption of near‐Infrared wavelengths has led to the common use of silicon single‐photon avalanche diodes (Si‐SPAD) for receiver systems. While the impacts of some SPAD properties on QKD have been explored extensively, the relationship of spot‐size and spatial position on the full instrumental response and thus quantum bit error rate (QBER) has been studied little. Changes in spot size and spatial position can result from atmospheric turbulence and pointing and tracking errors. Here, An empirical analysis of that relationship is presented utilising a large active area, 500 μm, free‐space coupled Si‐SPAD designed for free‐space QKD. A baseline full‐width at half‐maximum timing jitter of 182 ps and a QBER contribution of 0.1 % for a 1 GHz clock frequency QKD system and 100 ps time‐gating window are reported. The impacts of spot‐size and spatial position can increase the QBER to over 0.3%. The link between the spot‐size and timing jitter will allow the understanding of tolerancing for the alignment of Si‐SPADs within free‐space QKD receiver systems—an important factor in designing properly engineered practical systems and the equipment needed to compensate for atmospheric turbulence and pointing and tracking.

ASIC design of LZ77 compressor for computational storage drives

AbstractThe advent of cloud computing, 5G, and artificial intelligence technology has spurred the exponential growth of big data and the need for data compression. To alleviate the CPU burden, computational engines for data compression integrated into network cards and storage devices, giving rise to computational storage. However, computational storage faces several challenges, such as limited memory resources for large hash tables, data dependency for parallel encoding and decoding, and stringent requirements for bandwidth, latency, and power efficiency. Here, an application‐specific integrated circuit‐based LZ77 solution that aims to address these challenges is proposed. Our solution reduces the hash table resource consumption and the bandwidth fluctuations, while achieving high compression ratios. The solution is implemented using Taiwan Semiconductor Manufacturing Company Limited 12 nm technology and demonstrate that a single LZ77 engine can achieve a 4 GB/s throughput at 1 GHz clock frequency. By using four engines, a computational storage drive to achieve 16 GB/s compression bandwidth is enabled. The solution achieves a comparable compression ratio as the standard LZ77 algorithm with a negligible compression ratio loss of 5%, balancing efficiency and effectiveness.

64-GHz Operation of the Pseudorandom Binary Sequence Generator Using the Dual RSFQ/ERSFQ Standard Cell Library

A pseudo-random binary sequence of 7-bit word length (PRBS-7) generator has been designed as a low complexity circuit to validate the dual RSFQ/ERSFQ standard cell library, the circuit simulation methodology using process corners and Monte-Carlo statistical variations, as well as the digital design methodology using Verilog simulations with load-dependent timing back-annotation. The PRBS-7 design was optimized across multiple process corners with Monte-Carlo circuit simulations by incorporating statistical variations of the process parameters. To validate the digital design flow, the PRBS-7 was simulated using the Verilog behavioral descriptions of library cells. Using Liberty files for different global bias current (XI) process corners, the margins obtained from digital simulation were compared with circuit simulations. A 5 mm × 5 mm chip, incorporating both, the RSFQ and ERSFQ variant of the PRBS-7, was fabricated in the MIT-LL 100 μA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. The RSFQ variant of the PRBS-7 has been successfully tested up to 64.77 GHz clock frequency, and the ERSFQ variant up to 45.72 GHz clock frequency. In addition, we have analyzed the model-to-hardware correlation for RSFQ PRBS-7 for different clock frequencies. The simulations account for two process parameters, critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ).

50 GHz Operation of RSFQ Arithmetic Logic Unit Designed Using the Advanced Design Flow and the Dual RSFQ/ERSFQ Cell Library

Arithmetic Logic Unit (ALU) is an integral part of digital signal processing applications and computing systems. We used ALU, based on Kogge-Stone adder, as a reference circuit to experimentally validate the advanced design flow and the dual RSFQ/ERSFQ standard cell library. Using the advanced design flow, the ALU sub-blocks were optimized across multiple process corners using Monte-Carlo simulations incorporating statistical variations in the process parameters. The correct operation of ALU was verified in the digital HDL simulation using static timing analysis pre-fabrication. We designed the RSFQ 1-bit and 4-bit ALU using the standard cell library approach for MIT-LL 100 µA/µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. For the ERSFQ 1-bit ALU, the bias current overhead for the feeding JTLs was designed to be 100% of the ERSFQ DUT bias current. The RSFQ 1-bit ALU, designed for low frequency functional testing, demonstrated greater than ±15% bias margins. We demonstrated successful operation of the RSFQ 4-bit ALU with greater than ±6% bias margins at 20 GHz, greater than ±5% bias margins at 40 GHz, and greater than ±4% bias margins at 50 GHz clock frequency with BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The ERSFQ 1-bit ALU worked up to 30.72 GHz clock frequency with BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . In addition, we analyzed the model-to-hardware correlation for the INIT sub-block of the ALU. The simulations accounted for critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ) process parameters. We noted the discrepancy in simulated and measured margins and studied that a 15% higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> in simulations results in better model-to-hardware correlation for the INIT sub-block.

Power Optimization of 50 GHz ERSFQ Circuits

The Energy-efficient Rapid Single Flux Quantum (ERSFQ) logic family offers zero-static power dissipation. Any ERSFQ circuit requires a feeding Josephson transmission line (FJTL), a relatively large active transmission line, which serves as an accurate voltage source. For proper operation, the FJTL needs to be continuously pumped at a frequency that is equal to or higher than the highest clock frequency of the ERSFQ circuit. We selected an on-chip pseudo-random binary sequence (PRBS) generator as the example circuit since it naturally facilitates quantitative measurements of operating bias margins in terms of bit error rate (BER). Using external and internal flux pump sources, we performed extensive experimental studies on BER for ERSFQ PRBS generators operating at clock frequencies up to 50 GHz. We paid special attention to the over-pumping regime, where the FJTL pump frequency is higher than the PRBS clock frequency and confirmed its superiority in improving BER. At 35.56 GHz clock frequency, a group of 4 PRBS generators and 4 individual FJTLs with the bias current ratio (BCR) equal to 1, had a BER lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and bias margins of ±25% for internal and external flux pump sources over-pumping at 6.25% above clock frequency. The maximal operational clock frequency of a single ERSFQ PRBS generator with intrinsic pump source (+6.25% over-pumping) and BER <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> was 49.53 GHz. We also focused on optimization of the FJTL's size to reduce the power consumption and the area occupied by the FJTL itself. All chips were fabricated at MIT-Lincoln Laboratory using the SFQ5ee fab node. Future steps required for better understanding of ERSFQ operation are discussed.

High Performance Energy-Efficient Leakage-Tolerant Dual Keeper Pseudo Domino Logic

In this paper, an improved high performance energy-efficient leakage-tolerant dual keeper pseudo domino logic circuit is proposed. Circuit design methodologies such as pseudo domino, stacking effect and inverted clock-controlled dual keeper are used in the proposed work for significant reduction of the circuit’s propagation delay and leakage current. Using pseudo-domino logic voltage swing at the output is reduced, stacking effect reduces the leakage current and charge sharing issues in the circuit are reduced by an inverted clock-controlled dual keeper circuit. Leakage current in the proposed circuit is decreased by 21.9%, 20.8%, 71.6%, 52.4% and 57.5% to the conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic, respectively at a 27°C temperature and 1GHz clock frequency. Similarly, delay in the proposed circuit is reduced by 83.3%, 80.1%, 89.8%, 81.3% and 81.5% in comparison to conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic circuit, respectively. Performance metrics like power dissipation, delay, PDP, leakage current, static power, and EDP of the proposed circuit are analysed and compared with the existing domino logics. Monte-Carlo simulation is performed using 1000 samples to analyse the performance of the proposed circuit. The proposed logic circuit is also tested against temperature and process variations. The median values of the proposed buffer circuit’s power and delay are 5.6µW and 1.28ps, respectively and the standard deviation of average power and propagation delay are 633.62nW and 84.37fs, respectively at 27°C and 1GHz clock frequency.

A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity

In front of the offset, gain, timing, and bandwidth mismatch errors, time-interleaved analog-to-digital converters (TIADCs) are usually calibrated to achieve satisfying performance. In this paper, we propose a new digital calibration approach for TIADCs, including the direction-distance search algorithm and multiplier-free gradient descent method. Compared to state-of-the-art multiplication-less techniques, this approach significantly reduces time complexity by minimizing search space dimension, subtracting the number of searches, and varying iteration step size. Notably, no multiplier is needed in the mismatch estimation, resulting in a much lower computational complexity than in previous work. For a 12-bit 4-channel TIADC, simulation results show that the signal-to-noise-and-distortion ratio is improved from 25 dB to 65 dB within the duration of 1600 samples. The proposed calibration circuit is synthesized targeting standard 28-nm technology, occupying the area of 0.014 mm2 and dissipating the power of 19 mW at 2.8 GHz clock frequency.

BipBip: A Low-Latency Tweakable Block Cipher with Small Dimensions

Recently, a memory safety concept called Cryptographic Capability Computing (C3) has been proposed. C3 is the first memory safety mechanism that works without requiring extra storage for metadata and hence, has the potential to significantly enhance the security of modern IT-systems at a rather low cost. To achieve this, C3 heavily relies on ultra-low-latency cryptographic primitives. However, the most crucial primitive required by C3 demands uncommon dimensions. To partially encrypt 64-bit pointers, a 24-bit tweakable block cipher with a 40-bit tweak is needed. The research on low-latency tweakable block ciphers with such small dimensions is not very mature. Therefore, designing such a cipher provides a great research challenge, which we take on with this paper. As a result, we present BipBip, a 24-bit tweakable block cipher with a 40-bit tweak that allows for ASIC implementations with a latency of 3 cycles at a 4.5 GHz clock frequency on a modern 10 nm CMOS technology.

Guest editorial: Introduction to the special section on sustainable security solutions for Internet of Vehicles (VSI-iov)

A new current conveyor for Static Random Access Memory current sense amplifier is proposed for dual read bit-line cells. The first stage of sense amplifier is current conveyor that turns to a latch with substrate bias assistance, also reduces leakage during no sense period. Regenerative action is improved for faster latching action and operation at lower supply voltages. Simulation is performed using TSMC 65 nm, BSIM level 54 and results compared with the earlier suggested current sensing schemes. The proposed circuit consumes average power of 6.54µW for typical capacitance of 100fF bit-line and data-line capacitance and maximum power of 8.07μW at bit line capacitance as high as 200fF. Leakage current when sense amplifier is disabled, is only 80.4fA which is 2 × 10−5 × the latch-type circuit. The proposed circuit offers improved current sensitivity by 56% than the earlier suggested schemes and latching action at 0.2 V supply ensuring subthreshold SRAM operation. The delay of proposed circuit is just 12% of the conventional latch type circuit. Higher sensitivity of the proposed circuit ensures small memory cell size while maintaining basic stability and reliability. The proposed circuit was simulated for various memory sizes and 1 GHz clock frequency and exhibits reduced supply voltage operation, average power consumption, leakage power dissipation, immunity to temperature variation and memory size when compared with the earlier suggested sensing schemes.

A low leakage substrate bias-assisted technique for low voltage dual bit-line SRAM

A new current conveyor for Static Random Access Memory current sense amplifier is proposed for dual read bit-line cells. The first stage of sense amplifier is current conveyor that turns to a latch with substrate bias assistance, also reduces leakage during no sense period. Regenerative action is improved for faster latching action and operation at lower supply voltages. Simulation is performed using TSMC 65 nm, BSIM level 54 and results compared with the earlier suggested current sensing schemes. The proposed circuit consumes average power of 6.54µW for typical capacitance of 100fF bit-line and data-line capacitance and maximum power of 8.07μW at bit line capacitance as high as 200fF. Leakage current when sense amplifier is disabled, is only 80.4fA which is 2 × 10−5 × the latch-type circuit. The proposed circuit offers improved current sensitivity by 56% than the earlier suggested schemes and latching action at 0.2 V supply ensuring subthreshold SRAM operation. The delay of proposed circuit is just 12% of the conventional latch type circuit. Higher sensitivity of the proposed circuit ensures small memory cell size while maintaining basic stability and reliability. The proposed circuit was simulated for various memory sizes and 1 GHz clock frequency and exhibits reduced supply voltage operation, average power consumption, leakage power dissipation, immunity to temperature variation and memory size when compared with the earlier suggested sensing schemes.

Low Leakage Low Power Domino Logic Technique for Wide Fan-In Applications, 40-Bit Tag Comparator

Advances in sub-micron technologies make low power consumption and delay a major concern for present day systems. These parameters play a critical role in the performance of most widely used wide fan-in-dynamic logic gates. These wide fan-in dynamic gatesare employed in designing high speed tag comparators which are critical blocks of cache memory. The Stack-Scheme Clocked-Bleeder Domino (SS-CBD)tries to have an insight on a 40-bit tag comparator in terms of power consumption and noise immunity to produce a high-performancelogic style. The approach limits the voltage swing at the dynamic node with the helpof stack transistor employed between dynamic node and clocked bleeder transistor. This technique will reduce the overall power consumption and improves the gate speed for constant noise immunity. The observation is carried out with 1 GHz clock frequency and 0.9 V supply at 27 0C temperature using Cadence Virtuoso Spectre and Layout editor for GPDK 90 nm CMOS technology.

In-lab demonstration of coherent one-way protocol over free space with turbulence simulation.

Over the last decade, free-space quantum key distribution (QKD), a secure key sharing protocol, has risen in popularity due the adaptable nature of free-space networking and the near-term potential to share quantum-secure encryption keys over a global scale. While the literature has primarily focused on polarization based-protocols for free-space transmission, there are benefits to implementing other protocols, particularly when operating at fast clock-rates, such as in the GHz. In this paper, we experimentally demonstrate a time-bin QKD system, implementing the coherent one-way (COW) at 1 GHz clock frequency, utilizing a free-space channel and receiver. We demonstrate the receiver's robustness to atmospheric turbulence, maintaining an operational visibility of 92%, by utilizing a lab-based turbulence simulator. With a fixed channel loss of 16 dB, discounting turbulence, we obtain secret key rate (SKR) of 6.4 kbps, 3.4 kbps, and 270 bps for three increasing levels of turbulence. Our results highlight that turbulence must be better accounted for in free-space QKD modelling due to the additional induced loss.

A 0.13-μm CMOS resonator-based frequency-doubling mechanism for clock recovery in a full-rate 40 Gb/s optical receiver

A clock recovery circuit for a full-rate 40 Gb/s optical receiver is presented. The proposed circuit consists of a frequency doubling block, a mixer-based phase detector, and a 40 GHz voltage-controlled oscillator. The frequency doubling block, consisting of a tuned amplifier and a frequency doubler, adopts the LC-resonator loads, rather than the conventional resistive loads, which realizes operation at 40 GHz clock frequency. The circuit is fabricated in 0.13-μm CMOS technology. Measurement results indicate that the proposed circuit is able to recover a 40 GHz clock. The recovered clock frequency is at least 1.4 times higher than other competing circuits.

PITEM: Permutations-Based Instruction Tracking Via Electromagnetic Side-Channel Signal Analysis

The emergence of cyber-physical systems (CPS) and internet of things (IoT) devices impose significant security and privacy concerns that necessitate robust monitoring and malware detection systems. This paper proposes PITEM, a framework for instruction-level monitoring and malware detection using electromagnetic (EM) side-channels. PITEM identifies instruction types with similar EM emanations using hierarchical clustering. To track all combinations of these instruction types, we generate EM signatures for all permutations of them. In testing, we predict the permutation class of testing traces by a matched-filter-like predictor. We test the performance on two devices (FPGA-based and ARM-based) with 50 MHz and 1 GHz clock frequencies. We achieve 95.67% and 87.35% accuracies for these devices for single execution of permutations. We note that the accuracy increases to 100% when permutation blocks are repeated. Furthermore, we test the limits of the system by tracking permutations of instructions of the same type. With sufficient bandwidth and number of repetitions, individual instructions can be resolved with 87.5% and 95.78% accuracies for these devices. The performance is evaluated for different relative signal-to-noise ratio (SNR) levels and performance is stable for relative SNR values > 15 dB. Finally, we demonstrate PITEMs ability to detect fine-grained malware with 99.89% accuracy.

25-GHz Operation of ERSFQ Time-to-Digital Converter

Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 μW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

Design and Evaluation of 2-bit-Input Single-Flux-Quantum Autocorrelator System for Astronomical Data Analysis

To improve the accuracy of astronomical data analysis, an increase in the number of output bits from the A/D converter is effective. We investigated a single-flux-quantum (SFQ) autocorrelator and an integrator that supports multiple-bit signal output from an SFQ A/D converter for astronomical data processing. The SFQ binary counter was used as the integrator that decimates the output from the SFQ autocorrelator for communication with equipment at room temperature. We designed the test circuits composed of 2-bit inputs, an autocorrelator, and an integrator that contains 5631 Josephson junctions using the 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb process. We confirmed the correct operation of the test circuit with a normalized bias voltage margin of 102%-114% by the low-speed test. We obtained its correct high-speed operation up to a 55.1 GHz clock frequency. In terms of circuit design, scaling up the test circuit is easy. These results indicate the effectiveness of a high-precision and large-bandwidth radio astronomical observation using SFQ circuit technology.

Special issue on SoC and AI processors

Special issue on SoC and AI processors

Design and Implementation of a Single Flux Quantum Logic-Based Memory Controller for Josephson-CMOS Hybrid Memory Systems

Single flux quantum (SFQ) digital circuits have shown the potential for high speed/low power computation applications. Unfortunately, because of the low integration density and low driving capability of SFQ circuits, realizing large-scale memories by using only SFQ circuits is still a challenge. Josephson-CMOS hybrid memory, hybridizing high-speed, low power SFQ circuits, and high-density CMOS memories is already proposed as a solution to the large-scale memory problem in RSFQ digital systems. In this article, an SFQ-based memory controller which works up to 10 GHz clock frequencies is designed for Josephson-CMOS hybrid memory systems. The memory controller acts as a SFQ/CMOS interface between the SFQ circuit and SRAM module and generates the required waveforms for SRAM read and write operations. The circuit which has 4-b data and 2-b address lines is fabricated with AIST 2.5 kA/cm2 STP2 process and operations of the circuits are verified. To demonstrate the scalability of the circuit, memory controller was scaled to 8-b data and 13-b address to control of the 64kb SRAM. Operations of the scaled memory controller are verified with analog simulations. Scaled circuit consumes 0.76 mW power in an area of 1.64 mm × 1.60 mm.