GHz Clock Frequency Research Articles

15GHz low-voltage-swing carry-lookahead adder

We describe a high speed adder that employs a carry-lookahead structure and uses low-voltage-swing pass-transistor-based Manchester carry chain. This structure is implemented in 65nm technology and accommodates 15GHz clock frequency at the slowest corner which is 20% higher than the highest speed in the previously studied high-speed structures.

Differential pass transistor pulsed latch

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduces power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full swing of internal nodes. Also, the power consumption of the proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E × D by 45.5% over ep-SFF. The simulations were performed in a 0.13 um CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.

A New Energy x Delay-Aware Flip-Flop

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E × D by 45.5% over ep-SFF. The simulations were performed in a 0.1 μm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.

64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS

This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25 GHz clock frequency and its power/maximal frequency ratio is 151.4 μW/MHz.

Construction of an RSFQ 4-Bit ALU With Half Adder Cells

As part of the effort to develop a superconductive microprocessor, we constructed a rapid single flux quantum (RSFQ) 4-bit arithmetic and logic unit (ALU) in a pipelined structure. To speed up the circuit, we used a forward clocking scheme. The 4-bit ALU consisted of ten RSFQ Half Adders, four 2 /spl times/ 2 switches, and several D flip-flops. By commutating output ports of the half adder, we were able to produce AND, OR, XOR, and ADD functions. The 4-bit ALU was fabricated using the Korea Photonics Technology Institute's ten-level 1.0 kA/cm/sup 2/ Nb process. The size of the ALU was 3.0 mm /spl times/ 1.5 mm, fitting in a 5 mm /spl times/ 5 mm chip. The fabricated 1-bit ALU block was successfully tested at up to a 40 GHz clock frequency. The complete 4-bit ALU operated correctly at up to a 5 GHz clock frequency.

Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems

This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is ±1.5 × T CLK . Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.

BENCHMARK RESULTS FOR HIGH-SPEED 4-BIT ACCUMULATORS IMPLEMENTED IN INDIUM PHOSPHIDE DHBT TECHNOLOGY

High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double hetereojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.

Development of superconductor electronics technology for high-end computing

This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm−2, 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s−1, both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.

Features of new laser micro-via organic substrate for semiconductor package

An introduced new substrate technology for semiconductor packaging by flip chip bonding has featured with following design deliverables. The conductor line width is 25 μm and the space between the lines is 25 μm minimum at an escape point between flip chip pads. The thickness of dielectric layer is adjusted to obtain characteristic impedance with 50 Ω. A film resin for dielectric is applied to a base core sequentially with conductor plane alternately and laser-drilled micro-via hole is formed in the resin to connect conductor planes. UV-laser drill is employed to provide micro-via hole with 48 μm as drilled. The conductor layers are formed with copper pulse-pattern plating after electroless seed layer plating. The substrate passed JEDEC level-3 stress test and 10 GHz clock frequency possibility was demonstrated.

High-resolution ADC operation up to 19.6 GHz clock frequency

We have designed, fabricated and tested the second-generation (2G) design of a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC chip uses the phase modulation–demodulation architecture and on-chip digital filtering. The 2G ADC design has been substantially enhanced. Both ADC front-end modulator and demodulator, as well as decimation digital filter, have been redesigned for operation at 20 GHz. Test results of this 6000 Josephson junction 2G ADC chip at clock frequencies up to 19.6 GHz are described. These test results were compared to the results of ADC functional simulation using MATLAB.

Concurrent garbage collection using hardware-assisted profiling

In the presence of on-chip multithreading, a Virtual Machine (VM) implementation can readily take advantage of service threads for enhancing performance by performing tasks such as profile collection and analysis, dynamic optimization, and garbage collection concurrently with program execution. In this context, a hardware-assisted profiling mechanism is proposed. The Relational Profiling Architecture (RPA) is designed from the top down. RPA is based on a relational model similar to the relational database model. Instructions selected for profiling produce a record of information. A simple query engine examines these records for patterns, and performs simple actions on matching records. The power and flexibility of RPA is demonstrated by developing a concurrent generational garbage collector for Java. Detailed execution driven simulations show that this collector has an average runtime overhead of approximately 0.6%. The short pauses in the application required for synchronization with the garbage collector are at most 54 microseconds, given a 1GHz clock frequency.

Input and output interfaces between RSFQ and semiconductor circuits

Superconducting converters between RSFQ subsystems in the return-to-zero (RZ) mode and semiconductor electronics in the non-return-to-zero (NRZ) mode are conceived, simulated (SPICE, CADENCE) and optimized (ABAK) for data transmission at 10 GHz clock frequency and low power dissipation. An error correction scheme with a majority gate is used. RZ-to-NRZ converters with only 21 Josephson junctions are implemented with the 1 kA/cm 2 Niobium technology in Karlsruhe and tested successfully at 4.2 K and 500 MHz. Improvements in fabrication and instrumentation will enable measurements at microwave clock frequencies.

A NRZ-output amplifier for RSFQ circuits

Interfaces between RSFQ circuits in the Return-to-Zero (RZ) and semiconductor circuits in the Non-Return-to-Zero (NRZ) mode are developed for data transmission at about 10 GHz clock frequencies reducing the errors owing to a finite sampling jitter of conventional room temperature equipment. A prototype of a NRZ output interface with the Nb-Al/sub 2/O/sub 3/-Nb technology has been simulated, implemented and successfully tested at 100 MHz. The interface can easily be combined with a superconducting pulse amplifier for NRZ output signals in the range of several mV. Corresponding simulations and a layout of the amplifier are presented.

Cryogenically Cooled CMOS

The factors affecting the feasibility of cryogenically cooled CMOS are reviewed. This approach becomes more attractive as CMOS feature sizes shrink below 250 nm where chip performance is limited by interconnect characteristics. The impact of interconnects is demonstrated using a methodology for estimating interconnect-limited CMOS performance. The cryogenic behavior of normal and superconducting interconnects is reviewed. Cooling the best normal interconnect metals such as Al or Cu to 77 K can produce 9×lower resistivity. High-temperature superconductors can produce lower resistance at GHz clock frequencies, but would be difficult to produce on low dielectric substrates compatible with silicon technology. Performance doubling has been demonstrated for CMOS circuits operating at liquid nitrogen temperature. Comparable performance improvements may be expected down to below 100 nm if process technology is adjusted appropriately. In addition, dramatic increases in DRAM storage times result from exponential decreases in subthreshold leakage currents. Circuit reliability should increase correspondingly, apart from hot-carrier induced degradation. Thermally efficient packages and refrigerators are required for cryogenic CMOS. Microchannel heat exchangers can produce thermally efficient cryogenic packages. However, thermodynamic limits to refrigerator performance may make operation at higher cryogenic temperatures more attractive.

A robust single phase clocking for low power, high-speed VLSI applications

Power dissipation is becoming a prime design constraint in VLSI systems. The new key words for evaluating a design's performance are low power and high speed. This requires an overall system design review that considers suitable algorithms, architectures, circuits, and technology. In synchronous systems, the clocking network sets the frame that contains the whole design. It must be simple and robust. Power consumption in the clock distribution network has usually been a substantial part of the system total power consumption. New true single phase latches and flip flops are presented that are slope-insensitive, fast, and have data dependent power consumption. Flip flops are presented that work between DC and 1.7 GHz clock frequencies in a 1 /spl mu/m CMOS technology. Methods are given that result in power saving in the clock system by reducing the clock rate by half for the same data throughput on the system level.

Characterization and improvement of GaAs HEMT analog switches for sampled-data applications

This paper presents design consideration and experimental comparison of GaAs HEMT analog switches for high-speed and high-precision sampled-data applications. At first, basic pass-transistor switches fabricated in a 0.5-/spl mu/m GaAs HEMT technology are measured for characterization of transient errors induced due to clock-feedthrough and charge transfer. In order to improve the switch dynamic performances, a dual dummy transistor compensation technique is used and related driver circuitry is developed. On-wafer measurements demonstrate that the improved switch provides a significant reduction of the transient errors, a reasonable dynamic range, and a high isolation. The switch with a 0.53 pF load capacitor achieves a total harmonic distortion below -55 dB and -38 dB at 10 MHz and 1.0 GHz clock frequency, respectively. >

Chip layout design of a Josephson LSI circuit for examining high-speed operability by using a standard cell automatic placement and routing technique

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A track-and-hold circuit based on the nonlinear quasiparticle conductance of superconductor-insulator-superconductor junctions

A new high-speed track-and-hold circuit is proposed and demonstrated. The current in a large inductor follows the instantaneous signal in the track mode and is nearly stationary in the hold mode. Control of track or hold mode is by means of lateral, balanced injection through a bridge of superconductor-insulator-superconductor (SIS) junctions. The high resistance subgap state is used for tracking and the low differential resistance at the energy gap is used for holding. Experimental results using a 6 GHz clock and signal frequencies up to 3.2 GHz are reported. >

The Future Impact of GaAs Digital IC's

A review of digital GaAs IC technology and an assessment of its future impact on gigabit signal processing is presented. High-speed signal processing and computers will require MSI-complexity interface circuits capable of 1-10 GHz clock frequencies and LSI-complexity digital circuits operating in the 0.2-5 GHz range at tens of microwatts per gate. A wide range of applications exists for frequency counters, multiplexers, A/D converters, FFT's, microprocessors, and memories that operate at speeds significantly higher than on presently available circuits. Issues related to high-speed IC design such as power dissipation, packing density, capacitance effects, design rules, and intra- and interchip propagation delays are discussed.

Device and circuit trends in gigabit logic

Recent implementations of Gbs−1 integrated circuits are mentioned and used as the basis for a capability projection of the more promising technologies. After first describing the projection strategy, both the silicon and GaAs circuit families are assessed with regard to their performance limits. A shorter analysis of Josephson technology follows. For scaled down devices in silicon as well as several GaAs technologies, potential l.s.i. solutions with 2–3 GHz clock frequencies are prognosticated. The 3–6 GHz range should eventually be accessible to m.s.i. d.m.e.s.f.e.t. circuits, whereas GaAs s.d.f.l., j.f.e.t. and e.m.e.s.f.e.t. approaches promise v.l.s.i. complexity between 1 and 3 GHz. The range around 10 GHz appears to be solely a future domain of Josephson circuits (up to v.l.s.i).