Abstract
An introduced new substrate technology for semiconductor packaging by flip chip bonding has featured with following design deliverables. The conductor line width is 25 μm and the space between the lines is 25 μm minimum at an escape point between flip chip pads. The thickness of dielectric layer is adjusted to obtain characteristic impedance with 50 Ω. A film resin for dielectric is applied to a base core sequentially with conductor plane alternately and laser-drilled micro-via hole is formed in the resin to connect conductor planes. UV-laser drill is employed to provide micro-via hole with 48 μm as drilled. The conductor layers are formed with copper pulse-pattern plating after electroless seed layer plating. The substrate passed JEDEC level-3 stress test and 10 GHz clock frequency possibility was demonstrated.
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