Test Vector Generation Research Articles

Multi-level sequential circuit partitioning for test vector generation for low power test in VLSI

Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit testing models. In this paper, we present a multi-level graph partitioning algorithm for circuit partitioning, which will minimize the number of test vectors during a low power test in VLSI circuits. By reducing the number of test vectors, we can reduce the energy consumption during the test. Our experimental results with ISCAS bench mark circuits have shown that the power can be reduced up to 55%.

A unified solution to reduce test power and test volume for Test-per-scan schemes

This paper proposes a unified solution to reduce test power and test volume for test-per-scan schemes. With the self-testing using MISR and Parallel SRSG (STUMPS) architecture and the developed reconfigurable Johnson counter, the proposed test pattern generator (TPG) applies two transition sequences to all scan chains, and the primary inputs of the circuit under test (CUT) keep unchanged at most times. Therefore, the switching activities both in the combinational block and in scan chains can be reduced simultaneously. If the generated test vectors that do not contribute to fault coverage are filtered out, the remaining deterministic patterns show the favorable features of high compressible and low-test power. Simulation results on ISCAS'89 benchmarks demonstrate that the proposed TPG imposes negligible impact on test length and power overhead of the CUT.

Test Generation for Glitch Faults of Crosstalk Effects in Digital Circuits Based on Genetic Algorithm with Niche

The more signal path ways close to each other in digital circuits, the greater the coupling effects. The coupling effects can led to an increasing number of signal integrity related faults such as crosstalk faults. In this paper, the glitch faults of crosstalk effects are studied. First of all, the test vector generation using signal paths of circuits is given. Secondly, a new test method for crosstalk faults in digital circuits is presented, which is based on the genetic algorithm with niche. The test method can detect the maximal crosstalk effects, i.e. the test vectors to be produced is to switch a set of aggressors that maximizes the switching of total coupling effects. The test method is also used to produce the test vectors of multiple crosstalk faults. The experimental results show that the method proposed in this paper can get the test vectors of the multiple crosstalk faults if the faults are testable.

A hierarchically defined fault pattern generator using genetic algorithm

Test generation using fault algorithms is a complex procedure. This paper presents a hierarchical approach for test vector generation, which searches for a compact set of test patterns, in an otherwise large search space. Genetic algorithms (GAs) have been effective in solving many search and optimisation problems. Since test generation is a search process over a large vector space, it is an ideal candidate for GAs. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including population size, fitness function and mutation rate, as well as selection and crossover schemes. The search for fitter members is possible by modifying a reference table. The main focus in this paper is on the hierarchical expansion of the module into its constituent modules and the fault analysis would be performed only on those submodules which give faulty responses. The variable crossover and mutation rates help in not being trapped in local minima. The different award numbers allows us in focussing on those test sets which give superior detection possibilities with respect to others.

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects

Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.

A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions

We present a mutation-based validation paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, design error simulation, and model-directed test vector generation. We first present a control-based coverage measure that is aimed at exposing design errors that incorrectly set control signal values. We then describe MVP's high-level concurrent design error simulator that can handle various modeled design errors. We then present fundamental techniques and data structures for analyzing high-level circuit implementations and present various optimizations to speed up the processing of data structures and consequently speed up MVP's overall test generation process. We next introduce a new automatic test vector generation technique for high-level hardware descriptions that generates a test sequence by efficiently solving constraints on multiple finite state machines. To speed up the test generation, MVP is empowered by learning abilities via profiling various aspects of the test generation process. Our experimental results show that MVP's learning abilities and automated test vector generation effectiveness make MVP significantly better than random or pseudorandom validation techniques.

Dynamic current testing for CMOS domino circuits

In this paper, we propose a method for testing CMOS domino circuits using the transient power supply current. The method is based on monitoring and processing the transient current. We evaluate the effectiveness of this testing method through simulations of various domino circuits of different sizes. Moreover, we propose a normalising technique to mask the process variations effect associated with current testing. Furthermore, we present a test vector generation algorithm for testing large domino circuits, and develop and implement a clustering technique to improve the fault coverage of the test method when used with large circuits. The clustering algorithm divides the circuit into different clusters where each cluster is fed by a different power supply branch.

Automatic Constraint Based Test Generation for Behavioral HDL Models

With the emergence of complex high-performance microprocessors, functional test generation has become a crucial design step. Constraint-based test generation is a well-studied directed behavioral level functional test generation paradigm. The paradigm involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. However, automatic extraction of constraints from a given behavioral hardware design language (HDL) model remained a challenging open problem. This paper proposes an approach for automatic extraction of word-level model constraints from the behavioral verilog HDL description. The scenarios to be tested are also expressed as constraints. The model and the scenario constraints are solved together using an integer solver to arrive at the necessary functional test. The effectiveness of the approach is demonstrated by automatically generating the constraint models for: 1) an exclusive-shared-invalid multiprocessor cache coherency model and 2) the 16-bit DLX-architecture, from their respective Verilog-based behavioral models. Experimental results that generate test vectors for high level scenarios like pipeline hazards, cache miss, etc., spanning over multiple time-frames are presented.

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.

C-testable bit parallel multipliers over GF (2 m )

We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2 m ) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys® tools using UMC 0.18 micron CMOS technology library.

Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM

A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state space by exploiting an easy-to-traverse extended finite state machine (FSM) model has been described. The ATPG engine relies on learning, backjumping and constraint logic programming to deterministically generate test vectors for traversing all transitions of the extended FSM. Testing of hard-to-detect faults is thus improved. The generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows also to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs.

Application-Dependent Delay Testing of FPGAs

Testing of field-programmable gate array (FPGA) resources used for mapping a particular design (application-dependent testing) is a key factor in FPGA defect tolerance for yield enhancement and cost reduction as well as online testing in adaptive reliable computing. The majority of the FPGA real estate is dedicated to the interconnect network, and defects in the interconnects manifest themselves as delay faults. In this paper, a very thorough application-dependent interconnect delay testing technique is presented. Achieving a high coverage on path delay fault has been traditionally intractable for application-specific integrated circuits. However, by leveraging the reconfigurability of FPGAs, the presented technique is able to achieve 100% robust path delay coverage on all the paths in the design. This automatically results in 100% transition fault coverage. The required number of test configurations is two or four, depending on the structure of the design. Algorithms with linear time complexity are presented for automatic test configuration and test vector generation

Instruction-Based Self-Testing of Delay Faults in Pipelined Processors

Aggressive processor design methodology using high-speed clock and deep submicrometer technology is necessitating the use of at-speed delay fault testing. Although nearly all modern processors use pipelined architecture, no method has been proposed in literature to model these for the purpose of test generation. This paper proposes a graph theoretic model of pipelined processors and develops a systematic approach to path delay fault testing of such processor cores using the processor instruction set. The proposed methodology generates test vectors under the extracted architectural constraints. These test vectors can be applied in functional mode of operation, hence, self-test becomes possible. Self-test in a functional mode can also be used for online periodic testing. Our approach uses a graph model for architectural constraint extraction and path classification. Test vectors are generated using constrained automatic test pattern generation (ATPG) under the extracted constraints. Finally, a test program consisting of an instruction sequence is generated for the application of generated test vectors. We applied our method to two example processors, namely a 16-bit 5-stage VPRO pipelined processor and a 32-bit pipelined DLX processor, to demonstrate the effectiveness of our methodology

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers

Fast parallel multipliers that contain logarithmic partial-product reduction trees pose a challenge to simulation-based high-accuracy timing verification, since the reduction tree has many reconvergent signal branches. However, such a multiplier architecture also offers a clue as how to attack the test-vector generation problem. The timing-critical paths are intimately associated with long carry propagation. We introduce a multiplier test-vector generation method that has the ability to exercise such long carry propagation paths. Through extensive circuit simulation and static timing analysis, we evaluate the quality of the test vectors that result from the new method. Especially for fast multipliers with a pronounced carry propagation, the timing-critical vectors manage to stimulate a path, which has a delay that comes close to the true worst case delay. We investigate the complexity and run-time for the test-vector generation, and derive timing-critical vectors up to a factor word length of 54 bits.

Instruction-level test methodology for CPU core self-testing

TIS is an instruction-level methodology for processor core self-testing that enhances instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced with test instructions. Online testing can be accomplished without any performance penalty. TIS tests different parts of the processor and detects stuck-at faults. This method can be employed in offline and online testing of single-cycle, multicycle and pipelined processors. But, TIS is more appropriate for online testing of pipelined architectures in which NOP instructions are frequently executed because of data, control and structural hazards. Running test instructions instead of these NOP instructions, TIS utilizes the time that is otherwise wasted by NOPs. In this article, two different implementations of TIS are presented. One implementation employs a dedicated hardware modules for test vector generation, while the other is a software-based approach that reads test vectors from memory. These two approaches are implemented on a pipelined processor core and their area overheads are compared. To demonstrate the appropriateness of the TIS test technique, several programs are executed and fault coverage results are presented.

Functional test generation based on word-level SAT

Functional test generation coupled with symbolic simulation offers a good compromise between formal verification and numerical simulation for design validation. The generation of functional test vectors guided by miscellaneous coverage metrics can be posed as a satisfiability problem (SAT). While a number of efficient Boolean SAT engines have been developed for gate level designs, they are not directly applicable to behavioral and RTL designs containing significant arithmetic components. This paper presents two approaches that enhance the capability of functional test generation by preserving arithmetic operators in the design. They are based on word-level SAT techniques: (1) LPSAT, based on integer linear programming, and (2) CLP-SAT, based on constraint logic programming. The proposed SAT solvers allow to efficiently handle the designs with mixed word-level arithmetic operators and bit-level logic gates. The experimental results are quite encouraging compared to traditional CNF-based and BDD-based SAT solvers. The paper also suggests a method to build an integrated SAT solving framework where different SAT solvers work together to provide a more complete solution to functional test generation and other verification applications.

Application-Specific Bridging Fault Testing of FPGAs

In this paper, a new technique for testing the interconnects of any arbitrary design mapped into an FPGA is presented. In this technique, only the configuration of logic blocks used in the design is changed, and the structure of the design remains unchanged. The test vector and configuration generation problem is systematically converted to a Boolean satisfiability (SAT) problem, and state of the art SAT-solvers are exploited for test vector and configuration generation. Experimental results on various benchmark circuits show that only two test configurations are required to test for all bridging faults, achieving 100% fault coverage, with respect to the fault list. Moreover, test vector and configuration generation time is less than a second for all benchmark designs.

Testing layered interconnection networks

We present an approach for fault detection in layered interconnection networks (LINs). An LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. Switching elements (made of simple switches such as transmission-gate-like devices) are arranged in a cascade to connect pairs of layers. The switching elements of an LIN have the same number of switches, but the switching patterns may not be uniform. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires configuring the LIN multiple times. Using a graph approach, it is proven that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results in the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow such that the maximal degree can be iteratively decreased, while guaranteeing the existence of an appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 percent fault coverage of bridge faults a postprocessing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N/sup 4/WL), where N is the total number of nets, W is the number of switches per switching element, and L is the number of layers. Extensive simulation results are provided.

Design verification by test vectors and arithmetic transform Universal Test Set

We investigate methodology for simulation-based verification under a fault model. Since it is currently not feasible to describe a comprehensive explicit model of design errors, we propose an implicit fault model. The model is based on the arithmetic transform (AT) spectral representation of faults. The verification of circuits under the small errors in spectral domain is then performed by the universal test set (UTS) approach to test vector generation. The major result shows that, for errors whose AT has at most t nonzero coefficients, there exist the UTS test vector set of size O(n/sub 2//sup log t/). Consequently, verification confidence can be parameterized by the size of the error t, where at most O(n/sub 2//sup log t/) verification vectors are simulated to verify the absence of faults belonging to such an implicitly defined fault class. The experimental confirmation of the feasibility of verification using such UTS is presented, together with the relations between the arithmetic and Walsh-Hadamard spectra that bound the AT error spectrum and show that a class of small error circuits has small error spectrum. The proposed approach has the advantage of compatibility with formal verification and testing methods.

Switch-Level Test-Vector Generation for CMOS Combinational Logic

A method is proposed of test-vector generation for stuck-open and other faults in CMOS combinational circuits represented at the switch level. It consists in solving three problems: (1) Identify a stimulus that should be applied to the element under test. (2) Trace a path through which the response could reach an output node. (3) Find a set of input values that could drive internal nodes to logic levels determined in solving problems (1) and (2). The method is illustrated with an example.