Design verification by test vectors and arithmetic transform Universal Test Set

Abstract

We investigate methodology for simulation-based verification under a fault model. Since it is currently not feasible to describe a comprehensive explicit model of design errors, we propose an implicit fault model. The model is based on the arithmetic transform (AT) spectral representation of faults. The verification of circuits under the small errors in spectral domain is then performed by the universal test set (UTS) approach to test vector generation. The major result shows that, for errors whose AT has at most t nonzero coefficients, there exist the UTS test vector set of size O(n/sub 2//sup log t/). Consequently, verification confidence can be parameterized by the size of the error t, where at most O(n/sub 2//sup log t/) verification vectors are simulated to verify the absence of faults belonging to such an implicitly defined fault class. The experimental confirmation of the feasibility of verification using such UTS is presented, together with the relations between the arithmetic and Walsh-Hadamard spectra that bound the AT error spectrum and show that a class of small error circuits has small error spectrum. The proposed approach has the advantage of compatibility with formal verification and testing methods.