Design verification by using universal test sets

Beyin Chen Beyin Chen,J.E Chen,Chong Len Lee Chong Len Lee

doi:10.1109/ats.1994.367221

Design verification by using universal test sets

Beyin Chen Beyin Chen, J.E Chen + Show 1 more

https://doi.org/10.1109/ats.1994.367221

Copy DOI

Publication Date: Nov 15, 1994

Citations: 11

Affiliation: National Yang Ming Chiao Tung University, Chung Hua University

#Universal Test Sets #Stuck-at Fault Model + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach. >

Full Text

Paper version not known

Open DOI Link

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Similar Papers

Paper Title

Journal

Date

Author

View more papers

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.