Testable design of AND–EXOR logic networks with universal test sets

Abstract

This paper presents a testability enhancement technique suited for AND–EXOR based logic networks that facilitates easy detection of stuck-at and bridging faults by a universal test set. Both cascaded and tree implementations of the EXOR-part are considered. The AND–EXOR based circuit implemented with a cascaded EXOR-part requires a universal test set of size (2 n + 6) for an n-variable function implementation. For Generalized Reed–Muller (GRM) implementation, this test set detects all single stuck-at and bridging faults (both OR-type and AND-type) and also large number of multiple bridging faults. For an Exclusive-OR Sum-of-Products (ESOP) implementation, a few single bridging faults may remain untested under this test set, occurrence of which can be minimized by employing an appropriate design and layout technique. Next, it is shown that an AND–EXOR network with a tree-based EXOR-part can be tested for similar faults by a universal test set of size (2 n + 8). This paper also solves an open problem of designing a universal test for a tree-based AND–EXOR circuit. Since the EXOR-tree has depth of ( ⌈ log 2 s ⌉ + 1 ), where s is the number of product terms in the given AND–EXOR expression, this tree-based design reduces the circuit delay significantly compared to cascaded EXOR implementation. In both the cases, the test set can be stored in a ROM on-chip for built-in self-test (BIST) purposes. For several benchmark circuits, the universal test set is found to be much smaller in size than the ATPG-generated test sets.