Abstract
A field programmable logic array is presented which can be programmed. This FPLA uses one-transistor reprogrammable switches instead of fuses. The FPLA design presented here is also easily testable. In this design, the PLA is partitioned into two parts, which are tested independently. The delay is kept to a minimum for each test vector. Furthermore, parallelism is employed during testing, and thus minimal test time is obtained. It employs a universal test set of minimal length to detect all single crosspoint faults, stuck faults and bridging faults. This universal test set also covers the majority of multiple faults. The test set is simple and avoids test generation complexity. A user can reprogram and test the proposed PLA.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEE Proceedings E Computers and Digital Techniques
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
