Abstract
A field programmable logic array (FPLA) design is presented which is easily testable. The programmable logic array (PLA) is partitioned into two parts, which are tested independently. The delay is kept to a minimum for each test vector. Parallelism is employed during testing, and thus minimal test time is obtained. It employs a universal test set of minimal length to detect all single crosspoint faults, stuck faults, and bridging faults. This universal test set also covers the majority of multiple faults. The test set is simple and avoids test generation complexity. A user can reprogram and test the proposed PLA. >
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