Bridging fault detections for testable realizations of logic functions

Abstract

A method of devising a universal test set for detecting bridging faults in circuit testable realizations is investigated. The circuit realizations employed use an XOR gate tree construction and generalized Reed-Muller (GRM) expressions of logic functions. It is shown that all AND bridging faults and OR bridging faults in the circuit realization can be detected. The cardinality of the bridging faults test set is (2n+m), where n is the number of variables present in the logic functions, and m is the number of product terms in function expressions. Furthermore, a bridging fault testing method is given for the testable realization of the EXOR-sum-of-products (ESOP) expression of logic functions. The ESOP representations yield fewer product terms than GRM expressions.