Test Vector Generation Research Articles

Concatenated LFSR makes a weighted built-in logic block observation

The length of a test sequence is reduced when using random test vector sequences with a weighted probability, provided that the probabilistic distribution in the inputs of the circuit has been optimized using a suitable method. There are algorithms that determine the probabilistic distribution for the logic 1s in the inputs of the circuit under test. In this paper, we propose a circuit structure that allows generation of random test vectors with a weighted probability, and analysis of the response, using multiple input registers implemented as BILBO registers. Accordingly, we have proceeded with the incorporation of these BIST structures in different benchmark circuits, one of them being the ALU of a communication processor.

Cellular automata as a BIST structure for testing CMOS circuits

Two-patterns are required to test single stuck-open faults in CMOS circuits, while detection of multiple stuck-open faults requires the application of three-patterns. The regular, modular and cascadable structure of cellular automata (CA) has been proposed as a built-in self-test (BIST) structure for on-chip generation of two-pattern and three-pattern test vectors. An analytical tool has been developed to characterise the properties of CA as a test pattern generator for CMOS circuits. The conditions to generate exhaustive two-patterns and three-patterns of n-bits have been investigated. Based on matrix algebraic analysis, it is shown that a specific class of CA satisfying this condition can be employed as a BIST structure for testing CMOS circuits. A lower bound on CA size has been analytically established. Criteria for the selection of the most desirable CA structure have also been presented along with the experimental results for a set of real-life circuits.

Integrated Test Solutions for a System Design Environment

While the performance, density, and complexity of application-specific systems increase at a rapid pace, equivalent advances are not being made in making them more easily testable, diagnosable, and maintainable. Even though testability bus standards, like JTAG Boundary Scan, have been developed to help eliminate these costs, there exists a need for efficient hardware and software tools to support them. Hence, a testability design and hardware support environment for application-specific systems is described which provides a designer with a set of hardware modules and circuitry, that support these standards and software tools for automatic incorporation of testability hardware, as well as automatic test vector and test program generation.

Rapid migration to VLSI

The authors describe how the evolution of digital ASICs from first attempts to VLSI was accelerated in creating a 115000-gate equivalent array, in a 340-pin quad flat pack, within three generations. The first generation consisted of a 7800 gate eq. array containing the 'glue logic' for a MIL-STD-1553B, dual redundant serial bus. CAE workstations were used to create the design, and vendor-specific tools were used for final simulations only. The second generation fully embedded the 1553 into the array, along the control registers, timers, counters, interrupt prioritorization and control, memory management, and DNA control circuitry to support an Intel 80960 CPU. The third generation, a 115000 gate eq. array, added a second 1553, three UARTs, and two SDLC serial ports, permitting the creation of a stand-alone computer-I/O card in a single assembly. The third-generation ASIC was created from the second-generation netlist with the addition of vendor-supplied macro circuits, compiled circuits, and synthesized circuits. The utilization of a test vector generation language aided the design process. >

A data path approach for testing microprocessors with a fault bound: the MC68000 case

This paper presents an improved approach to data path testing for microprocessors. The proposed approach is based on the technique of Freeman 1; it utilizes stimulus (S-) and fault (F-) paths in the functional description of a microprocessor to generate test vectors in a knowledge based testing system 2 such that controllability/observability as well as any additional hardware for design-for-testability can be promptly assessed. The proposed approach to data path testing is used for testing the MC68000 microprocessor. A combination of fault models (functional, instruction and stuck-at) inclusive of a fault bound assumption is used to discriminate between control and non-control faults. A test set for the combinational functional units of the MC68000 is then generated and compared with a pseudo-exhaustive approach. A significant reduction in the number of required test vectors is accomplished.

Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.

A new approach on fault list handling for faster fault elimination and direct test vector generation

In this paper we present two techniques to select the order of the faults to be dealt by an ATPG system for combinational circuits. The first method is based on the determination of a set of faults on specific lines for which test generation with a classical “search and backtrack”. ATPG algorithm is not necessary. With a procedure equivalent to a line justification over a fanout free region, test vectors for the faults on these lines can be easily generated. This method also determines if those faults are undetectable or hard to detect before test generation is performed. The second one is an application of the well known concept of dominancy. Both methodologies lead to CPU time speed-up on a classical ATPG system. Benchmarks for these two approaches are also included.

On behavior fault modeling for digital designs

A critical aspect of digital electronics is the testing of the manufactured designs for correct functionality. The testing process consists of first generating a set of test vectors, then applying them as stimuli to the manufactured designs, and finally comparing the output response with that of the desired response. A design is considered acceptable when the output response matches the desired response and is rejected otherwise. Fundamental to the process of test vector generation is the assumption of an underlying fault model that is a model of the failures introduced during manufacture. The choice of the fault model influences the accuracy of testing and the computer CPU time required to generate test vectors for a given design. The most popular fault model in the industry today is the single stuck-at fault at the gate level that requires exorbitantly large CPU times for moderately complex digital designs. This article introduces new high-level behavior fault models that are associated with high-level hardware descriptions of digital designs. The derivation of these faults is based on the failure modes of the language constructs of the high-level hardware description language. Behavior faults include multiple input stuck-at faults and this article also reasons the nature of test vectors for such faults. The potential advantages of behavior fault modeling include early estimates of fault coverage in the design process prior to the synthesis of the gate-level representation of the design, faster fault simulation, and results that may be more comprehensible to the high-level architects. The behavior-fault-modeling approach is evaluated through a study of correlation of the results of behavior fault simulation of several representative digital designs with the results of gate-level single stuck-at fault simulation of equivalent gate-level representations.

A low-overhead scheme for testing a bit-level finite ring systolic array

Testing large VLSI circuits is a difficult and challenging problem for designers. Large unstructured circuits are often impossible to test. The number of test vectors also tend to be large and difficult to generate using automated tools for testing. In this paper, we have investigated the testing of systolic arrays built from a finite ring cell that has been proposed recently for digital signal processing functions. The cell has been shown to allow encoding, decoding and general inner product type computations for residue number system applications, with considerable advantages over equivalent binary implementation. As a further feature, we show, in this paper, that an array of such cells is remarkably easy to test for stuck-at faults. Generating test vectors for these arrays is also straightforward.

Product-oriented test-pattern generation for Programmable Logic Arrays

A Product-oriented test-pattern generation strategy for Programmable Logic Arrays (PLAs) is presented. First the personality of products is discussed. Products are divided into several categories to speed up the test generation. This strategy aims at generating a very compact test set for crosspoint defects through the following steps: 1) generate special test vectors for each category of products at the beginning of test generation. Each vector is capable of detecting a great amount of crosspoint defects; 2) generate test vectors for the defects which are not covered by the tests already generated. In this step, some heuristics are employed to accelerate test generation. Based on this strategy, a PLA test—pattern generation system is developed and the experimental results are analyzed.

Test generation for current testing (CMOS ICs)

Current testing is useful for testing CMOS ICs because it can detect a large class of manufacturing defects, including defects that traditional stuck-at fault testing misses. The effectiveness of current testing can be enhanced if built-in current sensors are applied on-chip to monitor defect-related abnormal currents in the power supply buses. Such sensors have proved effective for built-in self-test. However, current testing requires the use of a special method to generate test vectors. The authors describe this method, which differs from that for traditional voltage-oriented testing, and postulate a test-generation algorithm for both on-chip and off-chip current testing. The algorithm uses realistic fault models extracted directly from the circuit layout.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A simulation-based method for generating tests for sequential circuits

In a recent work of the authors (1987), a simulation-based directed search approach for generating test vectors for combinational circuits was proposed. In this method, the search for a test vector is guided by a cost function computed by the simulator. Event-driven simulation deals with circuit delays in a very natural manner. Signal controllability information required for the cost function is incorporated in a new form of logic model called the threshold-value model. These concepts are extended to meet the needs of sequential circuit test generation. Such extensions include handling of unknown values, analysis of feedback loops, and analysis of race conditions in the threshold-value model. A threshold-value sequential test generation program, TVSET, is implemented. It automatically initializes the circuit and generates race-free tests for synchronous and asynchronous circuits. >

On a new class of C-testable systolic arrays

This paper presents a new approach to constant (C) testability of systolic arrays. This approach differs from previous approaches, because it uses a cell-level functional characterization, i.e. it relates the characteristics of processing in a basic cell to the generation of the test sequence. This characterization is used to define a new class of testable systems, namely the functionally C-testable (FC) arrays. The sufficient conditions for an array to be FC-testable are presented. It is also shown that cells which operate using a signed number system with an even range (such as signed-magnitude and one's complement), are best suited for FC-testability. The proposed theory is applied to one-dimensional unilateral arrays which employ the inner product as the basic processing step. The proposed characterization provides an unifying criterion for C-testable systems (such as those using partition and one-step testability), while also achieving a simple test vector generation and an optimal order of complexity in the testing process.

Testing multiple-output CMOS combinational circuits

The logic transistor function testing method used for testing single-output CMOS combinational circuits is extended to cover multiple-output CMOS combinational circuits. An algorithm is developed to generate test vectors capable of detecting single and multiple transistor stuck-open/stuck-short faults. We consider single and multiple faults that have a combinational effect, i.e. only a single-input vector test is required. Techniques that enhance the analysis and the planning of testing strategies that best accommodate particular test requirements, such as output-pin limitations, are developed. Illustrations of a multiple-output CMOS combinational circuit are presented.

Test generation and fault detection for VLSI PPL circuits

This work describes a test generation package developed to utilize the special features of PPL arrays (a structured logic design methodology developed by the VLSI group at the University of Utah) to generate high fault coverage test vectors at a reduced computational cost. The test strategy assumes that one of the scan design techniques is used. A fault oriented test generation algorithm combined with a heuristic test generation algorithm are the essential ingredients of this package. The heuristic algorithm generates an initial set of test vectors which is verified against a predefined list of possible faults. A fault oriented algorithm is then used to generate test vectors that can detect faults not detected by this set. The fault oriented algorithm uses a modified D-algorithm which includes look ahead features and a new seven valued logic to improve the average speed of the test generation process. Fault coverages in the 90% range were obtained using the test vectors generated by this package. Test vectors generated by both algorithms can optionally be stitched into sequences in a way that does not compromise their fault coverage. This reduces the overhead in actual test application time by cutting down the number of the serial scan in/out operations.

Fundamentals of testability-a tutorial

A review is presented of electrical testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits. The relationships between the most commonly used fault models are explored. Various fault simulation methods are contrasted. The basic mechanisms used in test-vector generation are illustrated by examples. The importance of testability analysis as a guide to design and test generation is discussed. Algorithms for automatic test-pattern generation are summarized. >

Testing for stuck-at-faults in multiple output MOS combinational circuits

Abstract Recently, we have introduced a comprehensive model for detecting single and multiple faults for MOS combinational circuits based on the logic transistor function concept. In this paper, we extend our previous work to cover MOS combinational circuits that have multiple output lines. A new algorithm is developed which is used to generate test vectors that are capable of detecting single and multiple stuck faults in multiple output MOS combinational circuits. We also introduce a new concept where all the transistors in a specific circuit are realized into a number of transistor sets which alleviates the analysis and planning of a test strategy that accommodates a particular test requirement, i.e. detecting a certain transistor fault occurrence, or fits particular test restrictions, i.e. output line limitation. The advantages of this concept in design for testability is outlined. The relationship of fault coverage and output lines is also introduced and analysed.

A directed search method for test generation using a concurrent simulator

A description is given of the application of a concurrent fault simulator to automatic test vector generation. As faults are simulated in the fault simulator a cost function is simultaneously computed. A simple cost function is the distance (in terms of the number of gates and flip-flops) of a fault effect from a primary output. The input vector is then modified to reduce the cost function until a test is found. Experimental results are presented showing the effectiveness of this method in generating tests for combinational and sequential circuits. By defining suitable cost functions, it has been possible to generate: (1) initialization sequences; (2) tests for a group of faults; and (3) a test for a given fault. Even asynchronous sequential circuits can be handled by this approach.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Built-in self-test of a CMOS ALU

A technique is proposed for implementing BIST (built-in self-test) in a CMOS arithmetic and logic unit (ALU). The approach covers single stuck-open faults and all functional faults that do not induce memory effects. The specific fault set covered by the test includes: (1) all single stuck-open faults on n and p transistors anywhere in the ALU (F1 faults); and (2) all functional faults that affect any single-bit slice of the (F2 faults), a functional fault being any fault that changes one combinational function into another. Functional faults in multiple slices are also detectable, as long as they do not generate identical responses in all even-numbered or odd-numbered ALU slices. With common techniques for test vector generation and response-verification, this BIST implementation provides higher fault coverage with only a small increase in surface area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design for testability for future digital avionics systems

The authors describe an integrated testing approach called the Maintenance and Diagnostic System (MADS), which was developed for digital avionics systems using VHSIC and semicustom devices. Mission/operational requirements dictate high availability with capability to detect 98% of all faults and isolate 90% of these faults to a line replacement module (LRM) or 95% of the faults to two LRMs. MADS achieves these goals by defining a module maintenance node (MMN) chip set for each LRM in the system and the design for testability concepts for hardware. The MMN aids parallel, high-speed testing of LRMs, isolating the fault(s) to a module/chip level while incurring less than 10% overhead. It uses the concepts of scan set design, pseudorandom test vector generation, output response compression, and separate scan set loops to test the SSI-MSI logic on the LRM. It also stores interim test results and run-time fault information to isolate the hard-to-reproduce failures and performs verification of interchip and intermodule wiring.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>