Gbit Dynamic Random Access Memory Research Articles

A Low-<i>V<sub>t</sub></i> Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing

A gated sense amplifier (GSA) consisting of a low-Vt gated preamplifier (LGA) and a high-Vt sense amplifier (SA) is proposed. The gating scheme of the LGA enables quick amplification of an initial cell signal voltage (vS0) because of its low Vt and prevents the cell signal from degrading due to interference noise between data lines. As for a conventional sense amplifier (CSA), this new type of noise causes sensing error, and the noise-generation mechanism was clarified for the first time by analysis of vS0. The high-Vt SA holds the amplified signal and keeps subthreshold current low. Moreover, the gating scheme of the low-Vt MOSFETs in the LGA drives the I/O line quickly. The GSA thus simultaneously achieves fast sensing, low-leakage data holding, and fast I/O driving, even for sub-1-V mid-point sensing. The GSA is promising for future sub-1-V gigabit dynamic random-access memory (DRAM) because of reduced variations in the threshold voltage of MOSFETs; thus, the offset voltage of the LGA is reduced. The effectiveness of the GSA was verified with a 70-nm 512-Mbit DRAM chip. It demonstrated row access time (tRCD) of 16.4ns and read access (tAA) of 14.3ns at array voltage of 0.9V.

Thickness dependence of leakage currents in high-permittivity thin films

The leakage current through high-permittivity perovskite thin films in the nanometer range is of great technological interest because of the possible applications of these insulating films in future submicroelectronic devices such as dielectrics in Gbit dynamic random access memories or gate oxides in metal–oxide–semiconductor field-effect transistors. The experimental result of decreasing leakage current with decreasing thickness of the dielectric for the same externally applied field can be described by using a model combining thermionic emission at the electrode/dielectric interface and a low-mobility, high-permittivity dielectric with low-permittivity layers at the interfaces, the so-called dead layers.

A Proposed Architecture for Polarization-Switching D/A Converter (PDAC)

The integration of ferroelectric capacitors with very large-scale integrated (VLSI) circuits on semiconductor wafers has been commercially viable for about one and a half decades. The primary applications of ferroelectric integrated circuits have been oriented to non-volatile memories and Gigabit dynamic random access memories (DRAMs). One potential application for ferroelectric capacitors is polarization-switching digital-to-analog converters (PDACs). In principle, PDACs make use of ferroelectric switching; i.e., spontaneous polarization is used as a new medium for data conversion other than the conventional conversion media such as voltage, current and charge. PDACs are analogous to charge-redistribution data converters that make use of charge and are implemented with normal linear capacitors. In addition to using a novel data-conversion medium, polarization-switching data converters require a novel architecture for circuit implementation. Presented here is a proposed architecture for PDACs. SPICE simulations verify the functionality of an 8-bit bipolar PDAC.

유도결합 플라즈마를 이용한 PST 박막의 식각 특성

(Pb,Sr)TiO<TEX>$_3$</TEX>(PST) thin films have attracted great interest as new dielectric materials of capacitors for Gbit dynamic random access memories. In this study, inductively coupled CF<TEX>$_4$</TEX>/Ar plasma was used to etch PST thin films. The maximum etch rate of PST thin films was 740 <TEX>$\AA$</TEX>/min at a CF<TEX>$_4$</TEX>(20 %)/Ar(80 %) 9as mixing ratio, an RF power of 800 W, a DC bias voltage of -200 V, a total gas flow of 20 sccm, and a chamber pressure of 15 mTorr. To clarify the etching mechanism, the residue on the surface of the etched PST thin films was investigated by X-ray photoelectron spectroscopy. It was found that Pb was mainly removed by physically assisted chemical etching. Sputter etching was effective in the etching of Sr than the chemical reaction of F with Sr, while Ti can almost removed by chemical reaction.

Leakage current in thin-films Ta2O5 on Si – is it a limiting factor for nanoscale dynamic memories?

A critical review of leakage current values and reliability issues for Ta2O5 thin films as high-k storage insulators in gigascale dynamic random access memories (DRAMs) is presented. The challenges for reaching the leakage current limits allowable for 1–4 Gbit DRAMs are discussed. The implications for the conduction mechanisms in Ta2O5, and their dependence on the parameters of the system Ta2O5/Si, are presented. The results of high-temperature oxygen annealing on the conduction mechanism of r.f.-sputtered Ta2O5 are illustrated. A leakage current density as low as 10−8 A cm−2 at a 1 MV cm−1 applied field has been obtained. It is concluded that the dominant conduction mechanism in the intermediate fields (0.8–1.3 MV cm−1) can be effectively controlled by appropriate technological steps.

Metallorganic Chemical Vapor Deposition of TaOx N y as a High-Dielectric-Constant Material for Next-Generation Devices

Tantalum oxynitride films were deposited by metallorganic chemical vapor deposition. Pentaethoxytantalum the most widely used source gas for depositing was used as the source gas and as the reaction gas. The activation energy of the surface reaction was estimated to be 1.1 eV for a single-source deposition deposition), and to decrease to ca. 0.37 eV with the addition of over 50 sccm Deposition rate at the surface-reaction-controlled regime increased to 2.6 nm/min with 100 sccm but decreased upon adding more than 100 sccm of The overall deposition rate of the surface-reaction-controlled regime was as predicted by the Langmuir-Hinshelwood model. With an increase in both deposition temperature and flow rate, the TaON phase predominated over The dielectric constants of the as-deposited and -annealed films were 51 and 146, respectively. It is believed that films are attractive high-dielectric-constant materials for the next generation of gigabit dynamic random access memory devices. However, films exhibit relatively high current leakage densities of to at 1.0 MV/cm. A porous film microstructure was observed by transmission electron microscopy, and this seemed to be responsible for these high leakage currents. Further systematic optimization of the deposition and annealing processes is needed to produce a dense microstructure with a low leakage current level. © 2002 The Electrochemical Society. All rights reserved.

Conformal Platinum Thin Films Prepared by Chemical Vapor Deposition under High Oxygen Partial Pressure

Conformal deposition of platinum thin films by chemical vapor deposition using (methylcyclopentadienyl)trimethylplatinum as a liquid precursor, whose vapor was transferred by an argon carrier gas, is presented. Conformal coverages at thicknesses of less than 30 nm were obtained under the condition of high oxygen partial pressures and low temperatures. The surface morphology roughened and changed to a discontinuous grain growth when the film thickness and growth temperature were increased. The dense and smooth films with conformal coverage can be used in the storage nodes of capacitors in gigabit dynamic random access memories. © 2001 The Electrochemical Society. All rights reserved.

Recent progress in 1×x-ray mask technology: Feasibility study using ASET-NIST format TaXN x-ray masks with 100 nm rule 4 Gbit dynamic random access memory test patterns

This article discusses recent progress in 1×x-ray mask technology in Japan. Proximity x-ray lithography (PXL) using synchrotron radiation light with a wavelength of 0.7–1.0 nm can in principle provide as high a throughput as optical lithography, because PXL and optical lithography both employ photon beams and masks. A high-performance electron-beam mask writer called the EB-X3, suitable for PXL, has been developed by NTT under the Association of Super-Advanced Electronics Technologies (ASET) program. It has a reproducible image placement (IP) accuracy of less than 15 nm. We used the shaped-beam EB-X3 to fabricate 100 nm rule x-ray masks for the gate and contact/hole (C/H) layers of 4 Gbit dynamic random access memory (DRAM) test patterns. The ASET-NIST (National Institute of Standards and Technology) type masks consist of a 350-nm-thick TaBN absorber, a 3-μm-thick SiC membrane (27-mm square membrane area), a 1-mm-thick Si substrate, and a 6.63-mm-thick Pyrex glass frame. We have achieved an IP accuracy for 1×x-ray masks of less than 15 nm at both the gate and C/H levels. The mask-to-mask overlay accuracy between the gate and C/H masks is less than 20 nm; and after magnification correction, it is less than 10 nm. The critical dimension (CD) variations for 100 nm features measured in a 24-mm-square area are less than 100±6.0 nm at both levels. An overlay accuracy for PXL of better than 30 nm (|mean|+3σ) was obtained by the double-exposure method using the XRA volume-production x-ray stepper (Canon, Inc.) and 18 nm overlay ASET-NIST type x-ray masks (gate to contact). An IP reproducibility of less than 7 nm has been achieved for the EB-X3 itself (best data). The resist CD accuracy on the membrane for 4 Gbit DRAM patterns is better than 7 nm (Δ|mean|+3σ=6.6 nm). These data indicate that PXL has the potential for patterning 50 nm node devices with current tools.

Molecular design and development of photoresists for ArF excimer laser lithography

Positive-tone and negative-tone resists for ArF excimer laser lithography are developed from novel polymers, which are called functionally-integrated polymers having polar alicyclic units. The fundamental unit of the polymers is an acrylate having a tetracyclododecane group with a carboxyl end group, which satisfies a lot of the requirements of ArF resists. A typical monomer is carboxy-tetracyclo[4.4.0.12,5.17,10]dodecyl methacrylate. In 1996, we established 0.15-µm “positive” line-and-space patterns at 21.8 mJ/cm2 using an ArF exposure system (0.55 numerical aperture), which meet the design rule requirement for fabricating 1-gigabit dynamic random access memories (DRAMs). This fundamental polymer unit has also been used to develop negative-tone resists for ArF lithography. In 1999, we also established 0.13-µm “negative” isolated line pattern at 7.1 mJ/cm2 using an ArF exposure system which fulfills the design rule requirement for logic circuits combined with gigabit DRAMs. Copyright © 2000 John Wiley & Sons, Ltd.

Anisotropic etching of RuO2 and Ru with high aspect ratio for gigabit dynamic random access memory

Anisotropic RuO2 and Ru etching technology for gigabit dynamic random access memory has been developed using high density O2+10% Cl2 plasma in an inductively coupled plasma etching system. Under the conditions of low pressure, high gas flow rate, and large overetching times, we have demonstrated 0.2 μm wide patterns in 0.3-μm-thick RuO2/Ru films and 0.1 μm wide patterns in 0.45-μm-thick Ru films, both with an almost perpendicular taper angle of 89°.

Plasma enhanced chemical vapor deposition Si-rich silicon oxynitride films for advanced self-aligned contact oxide etching in sub-0.25 μm ultralarge scale integration technology and beyond

We intentionally introduced excessive Si during the SiOxNy film deposition in order to increase the etch selectivity-to-SiOxNy for advanced self-aligned contact (SAC) etching in sub-0.25 μm ultralarge scale integration devices. The SiOxNy layer was deposited at a conventional plasma enhanced chemical vapor deposition chamber by using a mixture of SiH4, NH3, N2O, and He. The gas mixing ratio was optimized to get the best etch selectivity and low leakage current. The best result was obtained at 10% Si–SiOxNy. In order to employ SiOxNy film as an insulator as well as a SAC barrier, the leakage current of SiOxNy film was evaluated so that SiOxNy may have the low leakage current characteristics. The leakage current of 10% Si–SiOxNy film was 7×10−9 A/cm2. Besides, the Si-rich SiOxNy layer excellently played the roles of antireflection coating for word line and bit line photoresist patterning and sidewall spacer to build a metal–oxide–semiconductor transistor as well as a SAC oxide etch barrier. The contact oxide etching with the Si-rich SiOxNy film was done using C4F8/CH2F2/Ar in a dipole ring magnet plasma. As the C4F8 flow rate increases, the oxide etching selectivity-to-SiOxNy increases but etch stop tends to happen. Our optimized contact oxide etch process showed the high selectivity to SiOxNy larger than 25 and a wide process window (⩾5 sccm) for the C4F8 flow rate. When the Si-rich SiOxNy SAC process was applied to a gigabit dynamic random access memory of cell array, there was no electrical short failure between conductive layers.

A Low Thermal Budget High Performance 0.25–0.18 µm Merged Logic Device and Dynamic Random Access Memory Application

Merged dynamic random access memory (DRAM) with logic technology has been widely investigated because of to its high on-chip memory bandwidth, low power consumption, customized memory size, and small footprint advantages. A low thermal budget 0.25–0.18 µm embedded DRAM technology has been developed to merge a high-performance logic device and high-density DRAM on the same chip. In this newly developed technology, shallow trench isolation, a triple well, TiSix polycide, titanium salicide, a self-aligned contact poly-via and a low thermal budget oxide-nitride-oxide (ONO) as well as Ta2O5 capacitor dielectrics used for 1 Gbit DRAM design, are being applied. A 32 Mbit synchronous DRAM macro was designed based on this technology and is proposed offered as a drop-in module for embedded DRAM applications.

Molecular design and development of photoresists for ArF excimer laser lithography

Positive-tone and negative-tone resists for ArF excimer laser lithography are developed from novel polymers, which are called functionally-integrated polymers having polar alicyclic units. The fundamental unit of the polymers is an acrylate having a tetracyclododecane group with a carboxyl end group, which satisfies a lot of the requirements of ArF resists. A typical monomer is carboxy-tetracyclo[4.4.0.12,5.17,10]dodecyl methacrylate. In 1996, we established 0.15-µm “positive” line-and-space patterns at 21.8 mJ/cm2 using an ArF exposure system (0.55 numerical aperture), which meet the design rule requirement for fabricating 1-gigabit dynamic random access memories (DRAMs). This fundamental polymer unit has also been used to develop negative-tone resists for ArF lithography. In 1999, we also established 0.13-µm “negative” isolated line pattern at 7.1 mJ/cm2 using an ArF exposure system which fulfills the design rule requirement for logic circuits combined with gigabit DRAMs. Copyright © 2000 John Wiley & Sons, Ltd.

Dielectric and Electrical Characteristics of Titanium-Modified Ta2O5 Thin Films Deposited on Nitrided Polysilicon by Metalorganic Chemical Vapor Deposition

Titanium-modified tantalum oxide thin films with a composition of (Ta2O5)0.922–(TiO2)0.078, and pure Ta2O5 thin films of 12 nm thickness were prepared on a nitrided poly-Si electrode by liquid source delivery metalorganic chemical vapor deposition at 390°C. The effective dielectric constant of the Ti-modified Ta2O5 thin films is higher than that of the pure Ta2O5 thin films whether they were crystallized or not. The highest value of the effective dielectric constant is 30.2 for the Ti-modified Ta2O5 thin films after being subjected to rapid thermal oxygen annealing (RTO) at 800°C for 30 s, but that of the pure Ta2O5 is only 22.4 under the same heat treatment conditions. Moreover, the former also has a high and stable insulating characteristic against bias voltage, i.e., a low leakage current of 1×10-8 A/cm2 can be maintained at 2.5 MV/cm after RTO at 850°C for 90 s. However, that of pure Ta2O5 only reaches 1× 10-7 A/cm2 under the same treatment conditions. The relationship of current versus time (I–t) measured at room temperature also reveals the superior insulating property of Ti-modified Ta2O5 compared to that of pure Ta2O5 thin films. An excellent leakage current characteristic along with high capacitance suggests that the Ti-modified Ta2O5 thin film is a more promising material than the pure Ta2O5 film for use in the fabrication of capacitors for G-bit dynamic random access memories.

High contrast chemically amplified 193 nm resist for gigabit dynamic random access memory generation

Four Gb dynamic access random memory (DRAM) cell patterns which have a 0.12 μm design rule were demonstrated by using a high contrast chemically amplified 193 nm positive resist and high resolution exposure. All critical layers of 4 Gb DRAM, such as isolation, word line, contact hole, bit line, and storage node, were successfully resolved with suitable focus margin. The dissolution contrast of the resist film and the slope of dissolution rate curve were much higher than those of conventional polyhydroxystyrene based chemically amplified KrF positive resist. Moreover, the dry etch resistance of the resist film for both the polysilicon etch and the oxide etch was better than those of KrF resist. These results indicated that this resist material has enough potential for practical use. Furthermore, the resist profile simulation showed that mass production of 4 Gb DRAMs can be achieved by a combination of a high contrast resist and a higher numerical aperture lens under annular illumination.

Development of An Accurate Optical Proximity Correction System for 1 Gbit Dynamic Random Access Memory Fabrication

In this paper, we demonstrate the feasibility of a refined one-dimensional (1D) optical proximity correction (OPC) method incorporated into a hierarchical mask data processing system. The correction accuracy was examined using experimental and lithography simulation by application to test patterns of a 1 Gbit dynamic random access memory (DRAM) metal layer. In the case of the 0.16 µm rule, the standard deviation of the refined 1D OPC was reduced to 9 nm, which is 70% of the standard deviation of 13 nm of the conventional 1D OPC method. The proposed OPC system, using an engineering workstation, succeeded in correcting the metal layer in a miniature model of a 1 Gbit DRAM within 2-4 days. Well-designed hierarchical management in the mask data processing system suppressed mask data volume expansion to within 4% compared to the data volume without OPC. These results suggest that the refined 1D OPC method is useful for the correction of 1 Gbit and future DRAM devices.

(Ba,Sr)TiO 3 thin films with conducting perovskite electrodes for dynamic random access memory applications

Interfaces and hence electrodes determine the performance of (Ba,Sr)TiO3 (BST) capacitors for ultralarge scale integration dynamic random access memories. Electrode materials forming a rectifying contact on BST drastically reduce the dielectric constant and hence the capacitance and charge storage density of the capacitor, when the dielectric thickness is reduced. This can limit the role of Pt as an electrode material for gigabit dynamic random access memories (DRAM). The conducting oxide, La0.5Sr0.5CoO3 (LSCO) with its perovskite structure, has structural and chemical compatibility with BST. Our results in LSCO/BST/LSCO capacitor show that the mechanism of conduction is not interface limited but predominantly bulk limited. A 75 nm BST film with LSCO electrodes shows a leakage current density of 1×10−7 A/cm2 at 1 V, 85 °C. The dielectric constant at 1 V, 105 Hz is 350, making LSCO a potential contact electrode for DRAM memories.

Plasma CVD of (BaSr)TiO3 dielectrics for gigabit DRAM capacitors

Electron cyclotron resonance (ECR) plasma chemical vapor deposition (CVD) of (BaSr)TiO3 dielectrics is reviewed. The oxygen plasma lowered the crystallization temperature and carbon contamination. (BaSr)TiO3 CVD process was developed under conditions of relatively low deposition rate of 1.1 nm/min and a relatively low deposition temperature of 550°C. Utilizing this process, we developed a gigabit dynamic random access memory (DRAM) capacitor technology involving the preparation of a thin (BaSr)TiO3 capacitor dielectric over a RuO2/Ru storage node contacting a TiN/TiSiX/poly-Si plug. The ECR plasma CVD enabled uniform deposition of gigabit-DRAM-quality (BaSr)TiO3 films on the electrode sidewalls. The storage node contact improved in endurance against oxidation, by fabricating the buried-in TiN/TiSiX plug (TiN-capped plug) under the RuO2/Ru storage node. (BaSr)TiO3 films with a small equivalent SiO2 thickness of 0.38 nm and a leakage current density of 8.5×10−7 A/cm2 at an applied voltage of 1.0 V, were obtained without any further annealing process. An equivalent SiO2 thickness of 0.40 nm on the RuO2 sidewall was also achieved. It is concluded that this technology has reached the requirements for gigabit DRAM capacitors.

Ultrathin Ta2 O 5 Film Capacitor with Ru Bottom Electrode

The characteristics of the ultrathin film capacitors with Ru bottom electrodes have been investigated. Ru films are deposited on by sputtering in 10% ambient, for the bottom electrode, and films are deposited by chemical vapor deposition using and . By plasma treatment at 400°C after thermal treatment at 700°C, excellent properties, are obtained such that the effective film thickness is 0.68 nm for 6 nm thick film and the leakage current is less than between the range of −2.1 and +1.8 V. The film with a Ru bottom electrode is one of the most suitable structures for Gbit dynamic random access memory capacitors.

Interfacial reaction in the poly-Si/Ta2O5/TiN capacitor system

For tantalum pentoxide capacitors in 1 Gbit dynamic random access memory, titanium nitride is adopted as the top electrode. After postannealing at temperatures higher than 750 °C, the capacitance of Ta2O5 reduces due to an interfacial reaction between TiN and Ta2O5. This was studied by high resolution electron microscopy and energy dispersive spectroscopy with a 1 nm electron probe. It is found that voids form along the interface between TiN and Ta2O5 and a large proportion of Ta dissolves into the TiN film. The origin of the reaction is concluded to be a large solid solubility of Ta in TiN. After Ta outdiffusion into TiN, vacancies agglomerate and form voids in Ta2O5 and thereby reduce its capacitance. Since the driving force of the reaction is the solid solubility of Ta in TiN, the amount of the reaction is affected by the thickness of the TiN films.