Gaussian Doping Research Articles

An InGaAs-based Fin-EHBTFET with a heterogate and barrier layer for high performance

This paper proposes a fin electron-hole bilayer tunneling FET with a heterogate and an InAlAs barrier layer (HBF-EHBTFET). The heterogate can suppress off-state leakage caused by point tunneling, while the InAlAs barrier layer prevents source–drain direct tunneling, significantly reducing the off-state current (I off). P-type Gaussian doping can not only solve the problem of the inability to generate a hole layer during device fabrication, but also reduce the turn-on voltage of line-tunneling, ultimately increasing on-state current and reducing average subthreshold swing (SS avg). By optimizing parameters of the heterogate and InAlAs barrier layer, HBF-EHBTFET can obtain I off of 2.37 × 10−16 A μm−1, SS avg of 17.97 mV dec−1, a cutoff frequency (f T) of 13.2 GHz, and a gain bandwidth product (GBW) of 1.58 GHz. Compared with traditional EHBTFET, HBF-EHBTFET exhibits a reduction in I off by four orders of magnitude, a decrease in SS avg by 65.27%, and an increase in f T and GBW by 78.59% and 93.62%, respectively.

Axially Non-Uniform Properties Effected Electro-Elastic Fields in Bended Piezoelectric Semiconductor Beams

This paper studied the effects of axially non-uniform material and non-uniform doping on the electro-elastic fields in bent piezoelectric semiconductor beams. The mathematical model is established based on the phenomenological theory of piezoelectric semiconductor and Euler’s beam theory. To solve the governing equations with variable coefficients, the differential quadrature method is adopted. As two representative structures, the pure bending beam and cantilever beam are studied, respectively. From the calculated results, it can be found the varied material properties changed the effective stiffness, as a result, all the field quantities are altered. Meanwhile, the symmetry of all field quantities in a pure bending beam is broken. Considering different Gaussian doping parameters [Formula: see text] and [Formula: see text], it can be observed that the distribution rule of perturbation carrier density becomes complex. The increment of [Formula: see text] broadens the width of optimum range-producing carriers, however, the increment of [Formula: see text] describes the moving of the optimum range from left to right. Importantly, the introduction of non-uniform doping breaks the limitation of perturbation carrier density in a cantilever beam with uniform material properties, the maximum value of perturbation carrier density does not appear at the fixed end only. The obtained results could be the guidance in designing high-performance electric devices.

Introduction of Gate-All-Around FET (GAAFET)

The Gate-All-Around Field-Effect Transistor (GAAFET) represents a significant advancement in integrated circuits technology, offering enhanced functionality compared to its predecessor, the Fin Field-Effect Transistor (FinFET). This paper provides a comprehensive overview of GAAEFT, its historical developments, current state, and recent developments. The introduction section mentioned the importance of changing from FinFET to GAAFET structures. The historical developments section traces the evolution of GAAFET technology, highlighting key milestones and breakthroughs. The current state section addresses the limitations of silicon-based microelectronics technology, including challenges related to heat dissipation, reliability, and fabrication processes. The subsequent section explores the development of GAAFET technology, with a focus on the latest techniques, such as gate stacking, oxidation, and asymmetric non-local lateral Gaussian doping, which aim to improve electrostatic performance, mitigate short-channel effects, and enhance threshold voltage control. This work reveals the potential for the current and future development of GAAFET technology and its potential for wider application in integrated circuits design and fabrication.

Investigating the effects of doping gradient, trap charges, and temperature on Ge vertical TFET for low power switching and analog applications

Influence of Gaussian doping in transistor regions, doping gradient step size (σ), interface trap charges (ITC), and temperature on DC, Analog, and Linearity performance of Ge-Vertical Tunnel FET (VTFET) is explored using Technology Computer-Aided Design. The DC transfer/output characteristics, ION/IOFF ratio, sub-threshold swing(S); and Analog/RF parasitic capacitances (Cgg, Cgs, and Cgd), transconductance (gm), cut-off frequency (ft), Transit time, efficiency, are examined with Doping Gradient in source & drain, σ variance up to 25 nm, and ITC variation from 1010–1012 cm−2 at Al2O3/Ge interface. Further, linearity parameters, such as gm3, VIP2, VIP3, IMD3, IIP3 &CP1-dB are estimated for optimum Ge-VTFET. For reliability analysis, Ge-VTFET is inspected with temperature deviation from 250 K to 375 K. The proposed Ge-VTFET with the doping gradient in drain and σ of 25 nm revealed excellent performance such as low S ∼ 58 mV/dec, high ION/IOFF ratio ∼ 3 × 105, gm ∼ 6.8 µS, ft ∼ 3.96 GHz, and outstanding reliability even under ITC and temperature deviations, proved Ge-VTFET to be an exceptional contender for low-power switching & analog applications.

Investigation of gain-filtering Yb-doped fibers with different gain-dopant doping ratios for high power amplifier

We presented an investigation on gain-filtering Yb-doped fiber for the mitigation of transverse mode instability (TMI). The gain-filtering Yb-doped fibers were fabricated by modified chemical vapor deposition (MCVD) combined with solution doping technique. Four gain-dopant diameter ratio fibers, entailing 100% doping, ∼73% doping, Gaussian doping, and ∼57% doping, presented similar parameters with the core/inner cladding diameter of ∼30/400 μm and core numerical aperture (NA) of ∼0.061. The laser performances of four fibers were demonstrated by a bidirectional pumping all-fiber amplifier. The TMI thresholds of 100%-doped, ∼73%-doped, Gaussian-doped, and ∼57%-doped fibers, were measured to be ∼1753 W, ∼3089 W, ∼3048 W, and over 3301 W, corresponding to the M2 factors of ∼1.52, ∼1.40, ∼1.45, and ∼1.32, respectively. The experimental results indicated that by reasonably tailoring the gain-dopant doping diameter, better gain-filtering effect was manifested, exactly as higher TMI threshold and more superior beam quality. This contribution could provide an effective approach for obtaining high-brightness Yb-doped fiber amplifiers based on gain-filtering effect.

Inverse Gaussian Doped Nanoscale Junctionless Gate All Around-based Biosensor

This article discusses the electrical properties of an Inverse Gaussian Junctionless Gate All Around (IG-JLT-GAA) field effect transistor for identifying neutral and charged bioanalytes. In this work, the inverse Gaussian doping profile enables the potent command of gate over charge in channel in the GAA structure, resulting in improved performance attributes such as OFF current, ON current, current ratio, subthreshold slope, drain-induced barrier lowering, threshold voltage, and transconductance for the proposed biosensor. The leakage current (OFF) is 10−17 A, and the drain current (ON) is 10−6 A, with their ratio of 10−11 fetched at K = 10. This article investigates the effect of varying dielectric constants of biomolecules immobilized in cavity reflects the enhancement in biosensor sensitivity due to the immobilization of high dielectric constant protein bioanalytes. The drain-induced barrier lowering (DIBL) and subthreshold swing (SS) are 4.4 mV/V and 60.6688 mV/dec, respectively, for K = 10. The estimated threshold voltage sensitivity (SVT ) for various dielectric constant biomolecules was found to be 9.7 and 110.5 mV for K = 1 and K = 10, respectively. Further, the performance of the biosensor using well-known biotin biomolecules with K = 2.63 is studied, and the result shows that the biosensor performs outstandingly in all performance attributes required for the detection of charged and neutral biomolecules.

Gaussian doping profile in the channel region: A technology booster for junctionless transistors

In this work, we have developed analytical models for the channel potential, threshold voltage and drain current for a cylindrical Gate-All-Around Junctionless Metal-Oxide-Semiconductor Field Effect Transistors (GAA-JLTs) with Gaussian doped channel region along the radial direction with uniformly doped source and drain regions. It has been found that the variation in doping parameters, such as, straggle, projected range and peak doping concentration, significantly affects the device characteristics such as threshold voltage, Ion/Ioff and so on and therefore, tuning them may bring about optimized device design, avoiding excessive leakage current yet maintaining high on-state current. The results obtained through our proposed analytical model are validated by ATLAS 3-D device simulator. Further, the variation of channel potential with doping parameters and bias potentials have been investigated. We have shown that by tuning the doping profile parameters together with the aspect ratio (AR) of a non-circular cross-sectional JLT, the threshold voltage and Ion/Ioff can be optimized along with reduction in DIBL. The effects of Gaussian doping on few figures-of-merit (FOMs), as applicable to analog domain, have also been analyzed. Computations with necessary discussions have been presented to explore the impact of key doping parameters on the linearity of GAA-JL devices.

Optimization of negative capacitance junctionless gate-all-around field-effect transistor using asymmetric non-local lateral Gaussian doping

Technology advancements directed towards Internet-of-Things (IoT) and wearable computing electronics applications are booming in low-power devices, which requires downscaling of power supply voltage without sacrificing the performance of the device. A negative capacitance junctionless gate-all-around field-effect transistor (NC-JL-GAAFET) is investigated using technology computer-aided design (TCAD) simulations to further suppress the short-channel effects and reduce power consumption. Lateral Gaussian doping (LGD), proposed for the NC-JL-GAAFET, is considered its main doping mode. An asymmetric structure with varying lengths of source/drain extension regions is introduced into non-local LGD NC-JL-GAAFET. The results reveal that the proposed device with a larger length ratio for drain extension region has a higher switching current ratio and lower subthreshold swing. Furthermore, the TCAD simulations validate that the electrical characteristics can be easily optimized by adjusting the ferroelectric (FE) layer thickness on the gate stack. Therefore, an asymmetric non-local LGD NC-JL-GAAFET provides a potential scaling solution for the next-generation low-power devices.

Analysis of subthreshold swing in junctionless cylindrical surrounding gate MOSFET using gaussian doping profile

Analysis of subthreshold swing in junctionless cylindrical surrounding gate MOSFET using gaussian doping profile

Quasi-analytical model of surface potential and drain current for trigate negative capacitance FinFET: a superposition approach

Negative capacitance (NC) obtained from the ferroelectric polarization switching is a widely adopted approach for the realization of low power, high-performance devices. In this paper, for the first time, we have developed a 3D quasi-analytical model for the surface potential and drain current of the trigate NC-FinFET using the superposition approach. Till date, only double gate (DG) uniformly doped NC-FinFET structures have been explored, which does not reveal the practicality of the device. Therefore, we perform an extensive device evaluation: (a) by solving the Poisson’s equation separately for the side gates (DG) and the top gate to acquire a complete model for trigate FinFET using the superposition principle; (b) to mimic the actual source/drain (S/D) doping, we included Gaussian doping in our proposed model; (c) with the incorporation of the laterally extended gate and S/D underlap. The model data are found in good agreement with the well-calibrated simulation data. We have taken the parabolic approximation method and appropriate boundary conditions to solve the Poisson’s equation.

Design of Optical Fiber Communication System Under Carrier Photodiode/Compact PCI Bus and Signal Data Modulation

This study was developed to design a high-speed and high-power uni-traveling-carrier photodiode (UTC-PD). Gaussian doping is adopted in the absorption layer, and a thin-doped cliff layer is introduced above the collection layer. The effects on the high-speed performance of UTC-PD are analyzed, and the thickness and concentration of absorption layer, cliff layer, and collection layer are optimized. Then, the carrier optical detector is used in optical fiber communication system, and a small pluggable SFP fiber module is used to realize the conversion of photoelectric signal. Based on the test requirements, the test platform of optical fiber communication system is built, and the CPCI bus based on PCI9054 is designed to communicate with the industrial computer. Meanwhile, a multi-polarization and high-order modulation scheme is designed for optical signal. The effects of transmission power, transmission distance, and optical signal-to-noise ratio (OSNR) on the transmission performance of orthogonal amplitude modulation (DP-16QAM, DP-32QAM) signals are analyzed by simulation. Simulation analysis shows that the optimized UTC-PD has improved its high speed and saturation, whose 3 dB bandwidth is up to 56 GHz, and responsiveness up to 0.28 A/W. In high-speed serial differential data transmission, the optical fiber communication system based on carrier optical detector/CPCI bus receives and sends reliably, and the error code value is always 0. Based on the signal modulation scheme in this study, the increase of OSNR can reduce the bit error rate (BER), and the bit error rate of 2A8P-16QAM and 4A8P-32QAM will decrease, that is, the signal transmission needs a higher optical signal-to-noise ratio.

Analysis of Subthreshold Swing of Symmetric Junctionless Double Gate MOSFET Using Gaussian Doping Profile

—The variation of subthreshold swing(SS) according to the projected range (Rp ) and standard projected deviation (σp ) was analyzed when the symmetrical junctionless double gate (JLDG) MOSFET was doped with Gaussian doping profile. For this purpose, the analytical SS model was presented. We compared with the TCAD results to turn out the validity of this model, and the SSs of this model agreed with those of TCAD. The effective conduction path and mean doping concentration affecting the SS were analyzed according to the Rp and σp . As a result, the SS increased as the Rp and σp increased simultaneously. The smaller the Rp and the larger the σp , the lower the SS. When Rp = 1.5 nm, it showed the SS below 100mV/dec without being affected by the change of σp or silicon thickness. When σp = 3nm, it was also 100mV/dec or less regardless of the change of Rp and silicon thickness. Keywords— Double gate, Junctionless, Subthreshold swing, Gaussian, Projected range, Standard projected deviation

Analytical Modeling of 3D NAND Flash Cell With a Gaussian Doping Profile

The incessantly increasing demand for highly dense storage medium in this era of big-data has led to the development of 3D NAND Flash memories. 3D NAND Flash based SSDs have revolutionized edge storage and become an integral part of the data warehouses and the cloud storage systems. The conventional 3D NAND flash memory with greater than hundred stacked word-line (WL) layers suffer from channel tapering and non-uniformity in the threshold voltage of cells in different WL layers which necessitates the use of different programming voltages for different WL layers and a complex error-correction circuitry. A non-uniform vertical (Gaussian) channel doping profile alleviates the threshold voltage non-uniformity and leads to a significant reduction in the complexity of the error-correction circuitry and a simple (uniform) programming scheme for all WLs. Although behavioral models have been proposed to utilize 3D NAND flash memory for circuit and system-level applications, an analytical model is important to understand the intricate details of the device physics and propose design guidelines for efficient cell design. To this end, in this paper, for the first time, we have proposed an analytical model for the characteristic length, surface potential and inner potential of the Macaroni-body 3D NAND flash cell with vertical Gaussian doping profile. A strong agreement between the analytical model and the TCAD simulations for different gate lengths (down to 25 nm), inner and outer radius, channel and oxide thickness of the 3D NAND flash cell validates the efficacy of the developed model.

Impact of Gaussian Doping on SRAM Cell Stability in 14nm Junctionless FinFET Technology

Impact of Gaussian Doping on SRAM Cell Stability in 14nm Junctionless FinFET Technology

A Physics Based Threshold Voltage Modeling of Trigate Junctionless FinFETs Considering Gaussian Doping

A Physics Based Threshold Voltage Modeling of Trigate Junctionless FinFETs Considering Gaussian Doping

Impact of Non-Uniform Doping on the Reliability of Double Gate JunctionLess Transistor: A Numerical Investigation

This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10−9 A to 4 × 10−11 A @ V gs = −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10−9 A @ V gs = −1 V for L S = L D = 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 1019 cm−3 but at the cost of significantly high off-state current (2 × 10−9 A @ V gs = 0 V) and tunneling current (2 × 10−8 A @ V gs = −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10−9 A @ V gs = −1 V), moderate lattice temperature (326) and better I on/I off ratio (243 × 108). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect.

Electrostatic and Dynamic Analysis of P+PNP Double Junction Type and P+PNPN Triple Junction Type Pinned Photodiodes

This paper explains the device structure and operation of image sensors and solar cells. Both are semiconductor devices operating with the same physical principle of detecting photons. A high efficiency of the photon to electron energy conversion is very much desired in both devices. Image sensors now use a very advanced and scaled down CMOS fabrication process technology to achieve high performance features such as the excellent short wave blue light sensitivity for good color reproduction, the low noise and the no image lag picture quality for filmless and mechanical free action cameras. On the other hand, solar cells are still now built with the primitive floating N+P single junction type photodiode to minimize the fabrication process cost but with very low energy conversion efficiency of about 20%. It is explained in details that the depletion region of the PN junction is not the only place where we can achieve photo electron and hole pair separations effectively. The short-wave blue light has only 1000 Å silicon crystal penetration depth. The pinned surface P+P Gaussian doping profile has a very important role to achieve a better photon to energy conversion efficiency, especially for the short-wave blue light. Electrostatic and dynamic behaviors of Pinned Surface P+PNP Double Junction type Dynamic Photo Transistor and Pinned Surface P+PNPN Triple Junction type Dynamic Photo Thyristor are analyzed in details. Both of them are shown to be expected to have much excellent photon-to-electron energy conversion efficiency.

Performance Improvement of Heterojunction Double Gate TFET with Gaussian Doping

A new Ge/SiGe heterojunction double-gate tunnel field effect transistor (DGT) model with hetero dielectric gate and Gaussian doping drain region is investigated for the first time. The introduction of heterojunction with hetero dielectric will reduce band-to-band tunneling (BTBT) leakage current while maintaining high mobility to enhance drain current and transconductance characteristics of the device significantly. Along with that, the combined effect of analytical drain doping profile (Gaussian) and hetero dielectric suppresses the ambipolar behavior. Different DC characteristics of the device like energy band analysis, electric field, drain current and BTBT generation rate are analyzed for the proposed structure. RF figure of merit for the HD-HJDGT-GD is express by analyzing its transconductance (gm), cut off frequency (fT), maximum oscillation frequency (fmax), gain bandwidth product (GBP) and transconductance frequency product (TFP). The outcome of the model under study is compared with conventional DGT. It is apparent from the analysis that the recommended model has better DC and RF performance, which makes this device worth studying to be used in high-frequency applications. TCAD simulation is performed by using Sentaurus 2D device simulator from Synopsys.

Design and Performance Evaluation of Sub-10 nm Gaussian Doped Junctionless SOI and SELBOX FinFET

In this paper influences of uniform and non-uniform doping on the performance of SOI and SELBOX FinFET at gate length of sub-7 nm are evaluated. Junctionless devices require very heavy and uniformly doped very thin channel. It adversely affects the performance such as reduction in on-current, increased off-current, and degradation in short channel behavior. Due to technical limitations, the doping profile becomes non-uniform in the vertical direction. In this simulation studies we use Gaussian doping profile in the vertical dimension to get non-uniform doping profile. The simulations are performed using Silvaco TCAD. Firstly, the performance of uniformly doped SOI and SELBOX Transistors are analyzed and compared. Furthermore, non-uniformly doped SOI and SELBOX FinFETs are analyzed and compared. Comparison is done on the basis of parameters ION, IOFF, ION/IOFF ratio, DIBL, VTH, and SS etc. The simulation results show that the multi-gate structure with SELBOX technology gives best results under non-uniform doping profile.

Laterally asymmetric channel-based tunnel fieldeffect transistors: design and investigation

ABSTRACT In this paper, we propose and simulate a lateral asymmetrically doped channel-based tunnel field-effect transistor. The impact of laterally asymmetric channel (LAC) on the performance of a Tunnel Field-effect transistor, along with a detailed comparison with a uniformly doped TFET (UD-TFET) has been studied. The proposed TFET has uniformly doped source and drain regions and the asymmetrically doped channel is realised by employing the Gaussian profile doping in the channel. The peak doping (NC) and the standard deviation (σ) of Gaussian doping profile used in the LAC-TFET channel are varied and their impact on the DC and AC performances is studied. It has been observed that the use of laterally asymmetric-doped channel in a TFET enhances its ON current (ION), transconductance (gm ) and the cut-off frequency (fT ), without increasing the OFF state current. At optimum values of NC and σ, the ION, g m and the f T are enhanced by more two order of magnitude in the LAC TFET. Hence, we propose that LAC-TFET can serve as a viable alternative to improve the DC and AC characteristics of TFETs.