Gaussian Doping Research Articles

DC and analog/RF performance optimisation of source pocket dual work function TFET

ABSTRACTWe investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n+ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.

Analytical Modeling and Simulation of Subthreshold Characteristics of Recessed-Source/Drain (Re-S/D) Silicon-on-Insulator MOSFETs with Gaussian Doping Profile

Analytical Modeling and Simulation of Subthreshold Characteristics of Recessed-Source/Drain (Re-S/D) Silicon-on-Insulator MOSFETs with Gaussian Doping Profile

Analytical subthreshold current modeling of nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a vertical gaussian doping profile

Based on the evanescent-mode analysis, an insightful study of the channel potential is performed for the nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a vertical Gaussian doping. And a two-dimensional (2D) analytical subthreshold current model is presented. The front and the back channel subthreshold currents are effectively derived using the inversion layer current density model which takes the Gaussian doping into account. The accuracy of the model has been verified by 2D numerical device simulations using Sentaurus Technology Computer-Aided Design (TCAD) from Synopsys. The model provides a deep understanding and can be instrumental for the nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a non-uniform doping profile operating in the subthreshold regime.

Performance analysis of undoped and Gaussian doped cylindrical surrounding-gate MOSFET with it's small signal modeling

The scaling of the solid-state devices are reaching its limit and it enhances the significant short channel effects. To overcome these problems, the surrounding-gate MOSFET is emerging as a promising structure and is a replacement of traditional MOSFETs. In this research work, authors have analyzed the performance of various parameters for the cylindrical surrounding-gate MOSFET using surface potential based approach and further transformation of variable technique to find the solution of the same differential equation. However, the modeling of terminal charge and trans-capacitance are also presented which is used for the circuit simulation. The influence of Gaussian doping (in vertical direction across the radius of the device) has been analyzed and solution of the surface-potential is derived based on the taylor series expansion.

Subthreshold Current and Swing Modeling of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

This paper proposes a new model for the subthreshold current and swing of the short-channel symmetric underlap ultrathin double gate metal oxide field effect transistors with a source/drain lateral Gaussian doping profile. The channel potential model already reported earlier has been utilized to formulate the closed form expression for the subthreshold current and swing of the device. The effects of the lateral straggle and geometrical parameters such as the channel length, channel thickness, and oxide thickness on the off current and subthreshold slope have been demonstrated. The devices with source/drain lateral Gaussian doping profiles in the underlap structure are observed to be highly resistant to short channel effects while improving the current drive. The proposed model is validated by comparing the results with the numerical simulation data obtained by using the commercially available ATLAS™, a two-dimensional (2-D) device simulator from SILVACO.

Analytic modeling of potential and threshold voltage for short-channel thin-body fully depleted silicon-on-insulator MOSFETs with a vertical Gaussian doping profile

We verify that one-dimensional (1D) Gaussian expression is an appropriate approximation of the vertical doping profile, which is obtained by combining perpendicular ion implantation and rapid thermal annealing (RTA), for short-channel thin-body (20–30 nm) fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. The two-dimensional (2D) potential distribution of the silicon film is derived by adopting the evanescent mode analysis method, in which the potential function is broken into 1D long-channel and 2D short-channel potentials. The threshold voltage model is represented by the minimum front- and back-surface potentials of the silicon film. The application of the threshold voltage model can be extended to a 12 nm channel length. The results obtained using the models match well with the 2D numerical simulation results obtained using the Synopsys Sentaurus Device™. They provide a feasible way of developing new 2D models for nonuniform nanoscale thin-body FD-SOI devices.

DC and analogue/radio frequency performance optimisation of heterojunction double‐gate tunnel field‐effect transistor

The electrostatic behaviour of the different configurations of n-type heterojunction double-gate tunnel field-effect transistor (HDGTFET) has been analysed. The analysis is based on the basics of the circuit elements such as drain current, transconductance, parasitic capacitances, cut-off frequency and gain bandwidth product. From the investigation carried out, it can be inferred that dual metal hetero-dielectric double-gate HDGTFET with gate underlap achieves both low standby power OFF state current and high performance at low supply voltage. The performance of the device having different configurations has been analysed for drain region having a uniform and Gaussian doping profile.

Investigation of the novel 4H[sbnd]SiC trench MOSFET with non-uniform doping floating islands

In this paper, a novel 4HSiC trench metal-oxide-semiconductor field-effect transistor (MOSFET) with non-uniform doping floating islands is proposed, using a Gaussian doping profile in the floating islands. The feature of the non-uniform doping floating island is that the doping concentration of upper part is higher than the lower part. The electric field between the floating island and drift region can be reduced by the decrease in the doping concentration of the lower part. At the same time, the high doping concentration for the upper part of the floating island is utilized, so that gate oxide layer at the sharp corner of the trench gate bottom cannot be broken down in advance. The simulation results indicate that the breakdown voltage of the novel structure can increase by 48%, compared with the structure with the uniform doping (6 × 1017 cm−3) floating island. Furthermore, the switching and gate charge characteristics of the UMOSFETs with uniform and Gaussian doping floating islands have been simulated using two simple switching circuits. The results indicate that changing the doping concentration of the floating islands has no negative effect on the switching characteristics.

Impactful study of dual work function, underlap and hetero gate dielectric on TFET with different drain doping profile for high frequency performance estimation and optimization

This manuscript presents a comparative study of different combination for the dual workfunction gate material, underlap and hetero gate dielectric tunnel field-effect transistors (TFET’s). Their performances have been analyzed in terms of ON-state current, ambipolar behaviour and RF response along with different drain doping profile. For this, the Dual work function of gate provides enhancement in ON-state current by reducing the tunnel barrier width at source/channel interface. Whereas, the underlap of gate is done near to the drain region, helps in reduction of ambipolar conduction by creating deficiency of hole for the conduction, which is major hurdle for TFET. Further, the combinations of the dual workfunction and underlap give combine advantages of both such as improve ON-state current and suppressed ambipolar current. Apart from this, the combination of hetero gate dielectric dual workfunction under lapping leads to superior device performance in terms of ON-state current and ambipolar behaviour. The use of hetero gate dielectric and Gaussian doping profile with gate underlap reduces the gate to drain capacitance that also improves the RF parameters of the device.

Comprehensive doping scheme for MOSFETs in ultra-low-power subthreshold circuits design

Devices for subthreshold circuits do not require halo and retrograde doping like conventional super-threshold devices. This will reduce the number of steps in the fabrication process, parasitic capacitance and substrate noise dramatically in the subthreshold devices. This paper introduces a new comprehensive doping scheme for the transistors in subthreshold circuits. The proposed doping scheme would bring doping changes in the source and drain areas along with the substrate and channel regions of the transistors. The proposed doping scheme is characterized by the absence of halos at the source and drain ends. We propose a Gaussian doping distribution inside the source and drain regions, and a low–high–low distribution across the depth of the transistor from the channel surface towards the body region. It also has a low–high–low doping distribution along the length of the transistor below the channel region. Results show that the optimized device with the proposed doping profiles would provide higher ON current (Ion) at smaller body bias condition. The analysis is performed by changing the doping profile, the body bias, and the gate–source voltage (Vgs) to observe the off-state current (Ioff), threshold voltage variation, magnitude of Ion/Ioff ratio, transconductance, and the output conductance with the proposed doping profiles.

Electric field distribution and voltage breakdown modeling for any PN junction

Purpose – Scientists and engineers have been solving Poisson’s equation in PN junctions following two approaches: analytical solving or numerical methods. Although several efforts have been accomplished to offer accurate and fast analyses of the electric field distribution as a function of voltage bias and doping profiles, so far none achieved an analytic or semi-analytic solution to describe neither a double diffused PN junction nor a general case for any doping profile. The paper aims to discuss these issues. Design/methodology/approach – In this work, a double Gaussian doping distribution is first considered. However, such a doping profile leads to an implicit problem where Poisson’s equation cannot be solved analytically. A method is introduced and successfully applied, and compared to a finite element analysis. The approach is then generalized, where any doping profile can be considered. 2D and 3D extensions are also presented, when symmetries occur for the doping profile. Findings – These results and the approach here presented offer an efficient and accurate alternative to numerical methods for the modeling and simulation of mathematical equations arising in physics of semiconductor devices. Research limitations/implications – A general 3D extension in the case where no symmetry exists can be considered for further developments. Practical implications – The paper strongly simplify and ease the optimization and design of any PN junction. Originality/value – This paper provides a novel method for electric field distribution analysis.

Analytical Modeling of Potential Distribution and Threshold Voltage of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

This paper reports a new two-dimensional (2D) analytical model for the potential distribution and threshold voltage of the short-channel symmetric gate underlap ultrathin DG MOSFETs with a lateral Gaussian doping profile in the source (S)/drain (D) region. The parabolic approximation and conformal mapping techniques have been explored for solving the 2D Poisson’s equation to obtain the channel potential function of the device. The effects of straggle parameter (of the lateral Gaussian doping profile in the S/D region), underlap length, gate length, channel thickness and oxide thickness on the surface potential and threshold voltage have been investigated. The loss of switching speed due to the drain-induced barrier lowering (DIBL) has also been reported. The proposed model results have been validated by comparing them with their corresponding TCAD simulation data obtained by using the commercially available 2D ATLAS™ simulation software.

Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping

In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source–channel junction, and this decreases the width of the depletion region, which improves the ON-current ( ${I_{\rm{\scriptscriptstyle ON}}}$ ) and the RF performance. Furthermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.

Design of broadband and high-output power uni-traveling-carrier photodiodes

In this paper, the bandwidth and saturation current of uni-traveling-carrier photodiode (UTC-PD) is investigated by using physics-based modeling. To further improve the performance, novel device structures are proposed. On the one hand, graded bandgap structure is employed in the absorption layer. It is shown that similar to the effect of graded doping method, the electric field in the absorption layer is increased, and thus the bandwidth is improved. Moreover, both the graded doping and graded bandgap structure are optimized. It is found that for the considered UTC-PD, combining use of the optimized graded doping and graded bandgap structure in the absorption layer leads to an improvement of 39.4% in bandwidth. On the other hand, linear doping profile and Gaussian doping profile are proposed to be used in the collection layer. It is shown that the distribution of electric field in the depletion region is improved, which leads to better saturation performance. For the considered UTC-PD, by using the optimized linear doping profile and the Gaussian doping profile, the improvement in saturation current is 18.7% and 25.8%, respectively.

Junctionless Tunnel Field Effect Transistor with Nonuniform Doping

In this paper, the dc performance of a double gate Junctionless Tunnel Field Effect Transistor (DG-JLTFET) has been further enhanced with the implementation of double sided nonuniform Gaussian doping in the channel. The device has been simulated for different channel materials such as Si and various III-V compounds like Gallium Arsenide, Aluminium Indium Arsenide and Aluminium Indium Antimonide. It is shown that Gaussian doped channel Junctionless Tunnel Field Effect Transistor purveys higher ION/IOFF ratio, lower threshold voltage and sub-threshold slope and also offers better short channel performance as compared to JLTFET with uniformly doped channel.

A Ge Ultrathin-Body n-Channel Tunnel FET: Effects of Surface Orientation

We theoretically investigated the surface orientation effects on the complex band structures and performance of a 5-nm ultrathin-body Ge n-channel double gate tunnel field-effect transistor. The Ge is an indirect bandgap material, and the direct band-to-band (BTB) tunneling rate in Ge is not appreciated. We use (001) and (011) Ge thin-body to project the X[001] and X[100] valley to the 2-D Brillouin zone center, and (111) Ge thin-body to project the L[111] valley pair to the zone center. The trajectory of imaginary k is the key factor for direct BTB tunneling, and we find that the imaginary k-axis of the projected L[111] valley of (111) Ge thin-body provides the best BTB tunneling rate among the three orientations. The direct bandgap of (111) orientation is lowest among the three orientations, which results in the thinnest tunnel barrier in (111) device. The drive current of (111) device is 4× higher than (011) device and 15× higher than (001) device. The (001), (011), and (111) devices have subthreshold slope substantially lower than thermal limit, however, only (111) device has an I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sub> (current at 60 mV/decade slope) value close to the desired limit. We use lower Gaussian doping in drain region to suppress ambipolar current. A 5× lower doping results in a 2× longer tunnel barrier at the drain-channel interface and more than two orders of magnitude suppression of ambipolar current.

Study of threshold voltage fluctuation caused by source and drain extensions doping variation of tri-gate fin-type FET using three-dimensional device simulation

The threshold voltage (Vth) fluctuation becomes an emergency problem in the design of integrated circuits using scaled silicon transistors. Since the Vth fluctuation caused by random dopant fluctuation (RDF) in the channel region becomes seriously large, the RDF-induced Vth fluctuation has been studied so far. Although the tri-gate fin-type field-effect transistor (FinFET) is promising owing to the RDF-free intrinsic channel, the Vth fluctuation caused by source and drain extensions doping variation (SDEDV) has not been investigated yet. Therefore, we studied the SDEDV-induced Vth fluctuation of the tri-gate FinFET by three-dimensional (3D) device simulation for the first time. It is demonstrated first that 3D simulation is required for possible accurate analysis. Then it is shown that the SDEDV based on Gaussian doping causes a large Vth fluctuation with a standard deviation of 4.2 mV in the case of the tri-gate FinFET. The origin of the SDEDV-induced Vth fluctuation is the broadening variation of the 3D Gaussian doping profile in the source–drain direction. This result indicates that the broadening suppression of impurity in the ion-implantation and annealing processes is very important for the SDEDV-induced Vth fluctuation.

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.

Design and analysis of high speed and high saturation uni-traveling-carrier photodetector

In this paper, an InP-based mesa-structure uni-traveling-carrier photodetector is designed. By adopting Gaussian doping scheme in the absorption layer and incorporating an appropriate cliff layer, high speed and high saturation current characteristics are both achieved simultaneously. For the device with a 14 μm2 active area, the simulated results indicate that the bandwidth reaches 58 GHz and DC saturation current increases up to 158 mA at a reverse bias of 2 V. Under high optical injection, the bandwidth degradation and current saturation are studied, which are caused by energy band shift and electric field collapse.

이중게이트 MOSFET의 채널도핑에 다른 문턱전압이하 전류 변화 분석

본 연구에서는 이중게이트 MOSFET의 채널도핑농도의 변화에 따른 문턱전압이하 전류의 변화를 분석하였다. 이를 위하여 이중게이트 MOSFET의 채널 내 전위분포를 구하기 위하여 포아송방정식을 이용하였으며 이때 전하분포함수에 대하여 가우시안 함수를 사용하였다. 전위분포는 경계조건을 이용하여 채널크기에 따른 해석학적인 함수로 구하였다. 가우시안 함수의 변수인 이온주입범위 및 분포편차 그리고 채널도핑농도 등에 대하여 문턱전압 이하 전류 특성의 변화를 관찰하였다. 본 연구의 전위모델에 대한 타당성은 이미 기존에 발표된 논문에서 입증하였으며 본 연구에서는 이 모델을 이용하여 문턱전압이하 전류 특성을 분석하였다. 분석결과, 문턱전압이하 전류는 채널도핑농도 및 가우시안 분포함수의 변수 등에 크게 영향을 받는 것을 관찰할 수 있었다. This paper analyzed the change of subthreshold current for channel doping concentration of double gate(DG) MOSFET. Poisson's equation had been used to analyze the potential distribution in channel, and Gaussian function had been used as carrier distribution. The potential distribution was obtained as the analytical function of channel dimension, using the boundary condition. The subthreshold current had been analyzed for channel doping concentration, and projected range and standard projected deviation of Gaussian function. Since this analytical potential model was verified in the previous papers, we used this model to analyze the subthreshold current. As a result, we know the subthreshold current was influenced on parameters of Gaussian function and channel doping concentration for DGMOSFET.