Gated Diode Structure Research Articles

Selective p- and n-Doping of Colloidal PbSe Nanowires To Construct Electronic and Optoelectronic Devices.

We report the controlled and selective doping of colloidal PbSe nanowire arrays to define pn junctions for electronic and optoelectronic applications. The nanowires are remotely doped through their surface, p-type by exposure to oxygen and n-type by introducing a stoichiometric imbalance in favor of excess lead. By employing a patternable poly(methyl)methacrylate blocking layer, we define pn junctions in the nanowires along their length. We demonstrate integrated complementary metal-oxide semiconductor inverters in axially doped nanowires that have gains of 15 and a near full signal swing. We also show that these pn junction PbSe nanowire arrays form fast switching photodiodes with photocurrents that can be optimized in a gated-diode structure. Doping of the colloidal nanowires is compatible with device fabrication on flexible plastic substrates, promising a low-cost, solution-based route to high-performance nanowire devices.

Analysis of the Interface Trap Density in SOI FinFETs with Different TiN Gate Electrode Thickness through Charge Pumping Technique

This work presents the analysis of the interface trap density in triple-gate silicon-on-insulator FinFET gated-diode structures with different TiN gate electrode thickness and fin widths by using the charge pumping technique. It is shown that a thicker metal gate corresponds with more traps. The fin width comparison shows that narrow fin devices exhibit a higher interface trap density due to the (110) sidewall contribution.

Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions

Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gate- controlled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained-Si/strained-Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained-Si/strained-Ge/relaxed Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> hetero- junctions is used to extract a valence band offset of 0.64 eV at the strained-Si/strained-Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low-operating-voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.

A Novel Trapping-Nitride-Storage Non-Volatile Memory Cell Using a Gated-Diode Structure With an Ultra-Thin Dielectric Dopant Diffusion Barrier

A novel trapping-nitride-storage nonvolatile memory cell by using a gated-diode structure is proposed. An ultrathin nitride layer is introduced between the n-type and p-type regions of the diode. This layer acts as a dopant diffusion barrier that well defines the junction location. Meanwhile, it is thin enough that charge carriers can flow through it via direct tunneling at low field as being sensed. Good program/erase characteristics and acceptable reliability are presented. Finally, using a low-bandgap material to enhance the sensing current is suggested along with the preferred device structure.

Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

Conventional charge pumping is demonstrated on triple-gate silicon-on-insulator FinFET gated-diode structures with varying fin widths. A simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density. A higher interface state density on the sidewalls is observed, which is attributed to higher fin sidewall roughness. The methodology is also demonstrated to be sensitive to fin sidewall surface crystallographic orientation. The technique presents a straightforward means of assessing the fin sidewall and topwall interface quality, which can then be directly correlated with both processing influences and reliability effects

A novel dynamic memory cell with internal voltage gain

A 2T1D dynamic memory cell with two transistors (T) and a gated diode (D) is presented. A gated diode is a two terminal MOS device in which charge is stored when a voltage above the threshold voltage is applied between the gate and the source, and negligible charge is stored otherwise. The gated diode acts as a nonlinear capacitance for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain of the internal stored voltage, higher signal margin, higher current drive and low-voltage memory operation. Details about the gated diode structure, its signal amplification, the memory cell circuits and the array structure, some hardware and test results are presented, followed by comparison to other memory cells and future directions.

A comparison of ionizing radiation and high field stress effects in n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors

n -channel power vertical double-diffused metal-oxide-semiconductor field-effect-transistor (VDMOSFET) devices were subjected to a high electric field stress or to a x-ray radiation. The current-voltage and capacitance-voltage measurements show that the channel-side interface and the drain-side interface are affected differently in the case of high electric field stress, whereas the interfaces are nearly uniformly affected in the case of x-ray radiation. This paper also shows that for the gated diode structure of VDMOSFET, the direct-current current-voltage technique measures only the drain-side interface; the subthreshold current-voltage technique measures only the channel-side interface; and the capacitance-voltage technique measures both interfaces simultaneously and clearly distinguishes the two interfaces. The capacitance-voltage technique is suggested to be a good quantitative method to examine both interface regions by a single measurement.

Dark currents in long wavelength infrared HgCdTe gated photodiodes

The fabrication of HgCdTe photodiodes using plasma-induced p-to-n type conversion for junction formation shows promise in improving array uniformity and device yields in comparison to more traditional fabrication technologies. Previously, characterization and analysis of the diode current-voltage (I–V) characteristics of fabricated devices have given indications that surface-leakage current mechanisms are limiting device performance. To further investigate the effectiveness of the surface passivation employed in the fabrication process, gated-diode structures have been fabricated. The gated-diode structure enables the semiconductor surface potential to be varied, thus allowing the characteristics of surface-leakage currents and their effect on device performance to be evaluated. The long wavelength infrared (LWIR) HgCdTe gated photodiodes used in this study have been characterized using I–V measurements for variable gate-bias voltage and variable temperature. Analysis of the experimental results indicates that plasma-induced type conversion produces an n (lightly doped)-on-p junction that is highly susceptible to a trapped positive charge in the passivation layer, which results in increased surface-tunneling currents. Modeling of the various dark-current mechanisms is used to show the effect on dark-current generation of the surface band bending induced by variations in surface potential. In addition, temperature-dependent I–V measurements and analysis have also been conducted.

Inversion behavior in Sc2O3/GaN gated diodes

The capacitance–voltage (C–V) characteristics of Sc2O3/p-GaN gate-controlled diodes show unusual hook shapes due to the charging of surface states. From the drain–voltage dependence of the C–V curves, the total surface state density was estimated to be ∼8.2×1012 cm−2 for diodes undergoing an implant activation anneal at 950 °C. The accumulation capacitance showed a significant dependence on measurement frequency and is suggested to result from the presence of an interfacial dielectric between the Sc2O3 and GaN. The Si-implanted n+ regions in the gated diode structure are effective in providing a source of inversion charge.

P-n junction peripheral current analysis using gated diode measurements

A modified method for analysis of the current–voltage characteristics of a gated diode structure is proposed and validated in order to investigate the peripheral reverse current in a silicon p-n junction diode. The peripheral generation current in modern p-n diodes is attributed fully to surface generation underneath the thick field oxide surrounding the structure, which typically contains a high density of interface traps. For a gated diode structure, the current region observed for large gate voltages, VG, is linked to the generation associated with the depletion at the Si-thick SiO2 interface. It will be shown that, compared to the classical analysis, this current step is a better alternative to assess the peripheral generation. The 25 times higher sensitivity of gated diode measurements in this mode allows one to reduce the test device perimeter and dimensions, without penalizing the measurement resolution for interface states. The main advantage of the proposed method is related to the fact that for the peripheral current extraction, only the measurement of one diode is needed instead of the tedious measurements and analyses of a set of diodes.

Leakage mechanisms in the heavily doped gated diode structures

A leakage current model is presented which shows very good agreement with reported experimental results on gated diode structures with contemporary ULSI dimensions. The leakage current is modeled as the Shockley-Read-Hall generation current, enhanced by the Poole-Frenkel effect and trap-assisted tunneling. The model shows very good agreement on gate voltage, temperature, and oxide thickness dependence for the normal operating voltage range. It is found from the model that the doping range from 2*10/sup 18/ to 1*10/sup 19/ cm/sup -3/ gives the most significant degradation to the leakage characteristics in trench-type DRAM cells and the drain of MOSFETs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Generation lifetime monitoring on high resistivity silicon using gated diodes

Abstract A stringent requirement for the high performance of electronic circuits is a low diode leakage current. This so-called dark current can be accurately described by means of two parameters, τ g , the bulk generation lifetime, and s , the surface generation velocity. In this paper it is shown that on high resistivity silicon, these two parameters cannot be derived as accurately or defined as uniquely from the classical MOS C−t measurements (Zerbst-technique), as is the case for standard doped silicon. The main reason for this is the fact that the boundary conditions for the measurement structure are no longer well defined. This causes physical parameters, which are normally neglected, to become important. Gated diodes on the other hand, when carefully designed, form a very well controlled structure. They allow the monitoring of the surface and the bulk defect density and defect energy level. Their behaviour can also be studied as a function of the processing sequence carried out, or the radiation dose the device was exposed to. Therefore gated diode structures are a major instrument to monitor the quality of silicon radiation detectors and to optimize their fabrication process. A for high resistivity silicon optimized device structure is proposed and its performance is illustrated with experimental results.

The effects of gate field on the leakage characteristics of heavily doped junctions

A gated-diode leakage-current mechanism is reported that is dominant below 4 V in ULSI (ultra-large-scale integration) gated-diode structures. The leakage mechanism has been fully characterized for gated junctions inherent in DRAM (dynamic random access memory) storage capacitor structures and the source-drain junctions of both PMOS (p-metal-oxide-semiconductor) and NMOS device structures. The salient features of the observed leakage current are that it is thermally activated and its magnitude increases exponentially with applied gate voltage. By making measurements at cryogenic temperatures it was possible to distinguish between the reported mechanism and that of band-to-band tunneling that occurs at higher applied voltages. A theoretical model is proposed that attributes the leakage mechanism to transport-limited thermal generation within the depleted space-charge region of the heavily doped side of junctions. An analytical expression derived from the proposed model is shown to be in excellent agreement with experimental results. >

Drain-avalanche and hole-trapping induced gate leakage in thin-oxide MOS devices

Leakage current components due to band-to-band tunneling and avalanche breakdown in thin-oxide (90-160 AA) gated-diode structures are discussed. Experimental results show that while the band-to-band tunneling current is not sensitive to channel doping concentration, the avalanche current is sensitive to channel doping concentration in the range of 10/sup 16/ to 10/sup 17/ cm/sup -3/. For oxides thicker than 110 AA, the gate current is found to be dominated by hot-hole injection and for oxides thinner than 110 AA the gate current is dominated by Fowler-Nordheim electron tunneling. After hot-hole injection, the gate oxide exhibits significant low-level leakage, which is explained by the barrier-lowering effect caused by the trapped holes in the oxide.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New results on electron injection, hole injection, and trapping in MONOS nonvolatile memory devices

Charge injection and trapping in silicon nitride layers are studied with the three-terminal metal-oxide-nitride-oxide-semiconductor (MONOS) gated-diode structure. A new experimental technique based on the linear voltage ramp is developed which measures electron and hole currents separately in the semiconductor during the actual charge injection (nonsteady-state measurement as opposed to the steady-state method) across the tunneling oxide. In addition, the technique measures the flat-band voltage shift and minimizes the back tunneling of the injected charge (a problem with the pulse measurement). The blocking oxide between the gate electrode and the nitride layer prevents any injection from the gate electrode. The main conclusion from these studies is that the semiconductor injects electrons and holes into the nitride layer for positive and negative polarities of the gate bias, respectively. This result is in sharp contrast with the existing interpretations based on a single-carrier type. It is speculated that the recombination of electrons and holes takes place in the nitride layer via an amphoteric trap. At small levels of charge injection, centroids of the trapped charge (measured from the tunneling oxide-nitride interface) for both electron and hole injection conditions are found to be located at 75-80 A at room temperature and 15-20 A at 100 K.

On the nonequilibrium statistics and small signal admittance of Si-SiO2 interface traps in the deep-depleted gated-diode structure

Nonequilibrium generation-recombination statistics are examined for the deep-depleted gated-diode structure. This structure eliminates the minority-carrier capture process and allows the competing emission process to dominate near the middle of the Si band gap. It is found that the steady-state occupancy function of the midgap interface traps deviates considerably from the Fermi–Dirac distribution which is applicable to the equilibrium situation. As a consequence of this deviation, rapid attenuation of the ac trap conductance with frequency for the midgap traps is predicted and experimentally verified. The ratio of electron to hole capture cross sections, R=σn/σp, has a pronounced influence on the trap energy associated with the onset of ‘‘pinning,’’ UTP=1/2(ln R).

Experimental verification of electron-hole recombination theory for Si-SiO2 interface traps with nonequilibrium, steady-state, admittance measurements

An analytical and experimental study of deep level Si-SiO2 interface traps is presented for small-signal, admittance measurements on a gated-diode structure. This technique eliminates the minority-carrier capture process and allows the competing emission process to dominate near the middle of the Si band gap. First-order rate kinetics has been employed to predict the behavior of the nonequilibrium, steady-state, occupancy function and ‘‘trap conductance’’ for states in the midgap region. Theory predicts and experimental measurements verify a sudden decrease or ‘‘pinning’’ of the trap conductance. The ratio of electron to hole capture cross sections, R=σn/σp, has a pronounced influence on the trap energy associated with the onset of ‘‘pinning’’, UTP= 1/2 ln(R).

The energy level of thallium in silicon

Thermal-emission-rate measurements, including DLTS, have been made on thallium-doped gated diode structures fabricated using an implanted thallium source. The rate of thermal emission was found to be strongly field dependent, giving results comparable to the prediction of the simple Poole-Frenkel model. The field-free trap separation from the valence-band edge was determined to be 0.24 eV, with a hole-capture cross section of 2.4×10−14 cm2.

Comparison of leakage currents in ion-implanted and diffused p-n junctions

Phosphorous diffused and arsenic ion-implanted p-n junctions have been prepared in 0.5- and 2-Ω cm p-type 〈100〉 Si wafers. Leakage currents have been measured on gated diode structures of various geometries as a function of bias voltage and temperature. From these measurements the relative importance of the surface, depletion layer, and bulk carrier generation to junction leakage have been determined. The leakage current levels measured on the ion-implanted junctions are comparable to those measured on the diffused junctions. The surface generation leakage component is the largest, ranging from 5×10−15–10−13 A/mil2 at 25 °C. This sufficiently large to dominate the leakage current for junctions with areas less than approximately 103 mil2. The depletion-layer generation current IDB is much smaller than would be expected. It is only comparable to the diffusion current at 25 °C where IDB?IDIFF?10−16 A/mil2 for defect-free junctions. IDIFF becomes the largest for large-area diodes or for junctions of any area at higher temperatures. The dependence of the leakage current on junction reverse bias and gate bias voltage is stronger than would be predicted for growth in the depletion-layer thickness with bias. We observe IL∼Vn with n∼1–2. This enhanced leakage occurs at the junction perimeter and is associated with increased perimeter electric fields.