Abstract
A modified method for analysis of the current–voltage characteristics of a gated diode structure is proposed and validated in order to investigate the peripheral reverse current in a silicon p-n junction diode. The peripheral generation current in modern p-n diodes is attributed fully to surface generation underneath the thick field oxide surrounding the structure, which typically contains a high density of interface traps. For a gated diode structure, the current region observed for large gate voltages, VG, is linked to the generation associated with the depletion at the Si-thick SiO2 interface. It will be shown that, compared to the classical analysis, this current step is a better alternative to assess the peripheral generation. The 25 times higher sensitivity of gated diode measurements in this mode allows one to reduce the test device perimeter and dimensions, without penalizing the measurement resolution for interface states. The main advantage of the proposed method is related to the fact that for the peripheral current extraction, only the measurement of one diode is needed instead of the tedious measurements and analyses of a set of diodes.
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