Gate Voltage Swing Research Articles

High performance InGaN double channel high electron mobility transistors with strong coupling effect between the channels

In this paper, high performance InGaN double channel (DC) high electron mobility transistors (HEMTs) are proposed and systematically investigated. Due to the coordination of double InGaN channels, a large maximum drain current density and a distinct double-hump feature of the transconductance and frequency performance are achieved. More importantly, it is revealed that the coupling effect between the two InGaN channels is much stronger than that of the conventional GaN DC HEMTs. This characteristic leads to a remarkable enhancement in the gate voltage swing, indicating the excellent linearity of the InGaN DC HEMTs at both dc and rf conditions. Benefiting from the enhanced electron confinement in InGaN channels, the fabricated HEMTs show a low off state drain leakage current of 0.26 μA/mm and a high on/off current ratio (Ion/Ioff) of 5.1 × 106. In addition, the desirable current collapse and breakdown characteristics are also obtained. This work convincingly demonstrates the great potential and practicality of the InGaN DC HEMTs for high power and high bandwidth applications.

An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances

This paper details the theory and implementation of an inverse-class-F (class- $\text{F}^{-1}$ ) CMOS oscillator. It features: 1) a single-ended PMOS-NMOS-complementary architecture to generate the differential outputs and 2) a transformer-based two-port resonator to boost the drain-to-gate voltage gain ( $A_{\mathrm {V}}$ ) while creating two intrinsic-high- ${Q}$ impedance peaks at the fundamental ( $f_{\mathrm {LO}}$ ) and double (2 $f_{\mathrm {LO}}$ ) oscillation frequencies. The enlarged second harmonic voltage extends the flat span in which the impulse sensitivity function (ISF) is minimum, and the amplified gate voltage swing reduces the current commutation time, thereby lowering the – $g_{\mathrm {m}}$ transistor’s noise-to-phase noise (PN) conversion. Prototyped in 65-nm CMOS, the class- $\text{F}^{-1}$ oscillator at 4 GHz exhibits a PN of −144.8 dBc/Hz at a 10-MHz offset, while offering a tuning range of 3.5–4.5 GHz. The corresponding figure of merit (FoM) is 196.1 dBc/Hz, and the die area is 0.14 mm2.

Phosphorene source engineered stacked metal gate tunnel field effect transistor with enhanced scaling

In this simulation based study, we report a tunnel field effect transistor on SOI substrates with phosphorene as source material to enhance the scaling of Si CMOS technology. The proposed device has been evaluated in the form of two design concept (lateral as well as vertical tunneling) and compared with its counterpart of Germanium source and silicon based conventional devices. Electrostatic doping is utilized in place of conventional chemical doping in the active medium, source and drain. This heterostructure tunnel FETs boots the conduction current significantly and reduced the supply voltage by unique thickness dependent properties of phosphorene. The proposed TFET found a wonderful energy efficient (10−2 fJ switching energy) steep switching device (∼0.1 mV/dec of point subthreshold swing) for future CMOS scaling with ∼109 on-to-off current ratio with 150 mV gate voltage swing and expected for sub-0.2 V operation at ≥1 GHz frequency.

Planar Nanostrip-Channel Al2O3/InAlN/GaN MISHEMTs on Si With Improved Linearity

In this work, a 100 nm-gate Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /InAlN/GaN metal-insulator-semiconductor high electron mobility transistor (MISHEMT) with a planar nanostrip-channel was fabricated on a Si substrate and its DC, small-signal RF and two-tone intermodulation characteristics were measured. The use of a planar nanostrip-channel and MIS structure allows these devices to have close to 10 dB better intermodulation distortion than traditional InAlN/GaN high electron mobility transistors. In addition, the GaN planar nanostrip-channel MISHEMT shows five orders of magnitude lower gate current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> , 30% higher current drivability and much improved g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> gate voltage swing than a planar nanostrip-channel GaN HEMT with a Schottky gate. This allows the planar nanostrip-channel GaN MISHEMT to be able to operate at higher input gate voltage (more than V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = +4 V) and achieve higher output current with better linearity performance.

Anomalous single-electron transfer in common-gate quadruple-dot single-electron devices with asymmetric junction capacitances

In this paper, anomalous single-electron transfer in common-gate quadruple-dot turnstile devices with asymmetric junction capacitances is revealed. That is, the islands have the same total number of excess electrons at high and low gate voltages of the swing that transfers a single electron. In another situation, two electrons enter the islands from the source and two electrons leave the islands for the source and drain during a gate voltage swing cycle. First, stability diagrams of the turnstile devices are presented. Then, sequences of single-electron tunneling events by gate voltage swings are investigated, which demonstrate the above-mentioned anomalous single-electron transfer between the source and the drain. The anomalous single-electron transfer can be understood by regarding the four islands as “three virtual islands and a virtual source or drain electrode of a virtual triple-dot device”. The anomalous behaviors of the four islands are explained by the normal behavior of the virtual islands transferring a single electron and the behavior of the virtual electrode.

Comparative Study on Graded-Barrier AlxGa1−xN/AlN/GaN/Si Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistor by Using Ultrasonic Spray Pyrolysis Deposition Technique

Comparative study on a novel Al2O3-dielectric graded-barrier (GB) AlxGa1−xN/AlN/GaN/Si (x = 0.22 ∼ 0.3) metal-oxide-semiconductor heterostructure field-effect transistor (MOS-HFET) formed by using the ultrasonic spray pyrolysis deposition (USPD) technique has been made with respect to a conventional-barrier (CB) Al0.26Ga0.74N/AlN/GaN/Si MOS-HFET and the reference Schottky-gate HFET devices. The GB AlxGa1−xN was devised to improve the interfacial quality and enhance the Schottky barrier height at the same time. A cost-effective ultrasonic spray pyrolysis deposition (USPD) method was used to form the high-k Al2O3 gate dielectric and surface passivation on the AlGaN barrier of the present MOS-HFETs. Comprehensive device performances, including maximum extrinsic transconductance (gm,max), maximum drain-source current density (IDS,max), gate-voltage swing (GVS) linearity, breakdown voltages, subthreshold swing (SS), on/off current ratio (Ion/Ioff), high frequencies, and power performance are investigated.

Fabrication of high-performance InGaZnOx thin film transistors based on control of oxidation using a low-temperature plasma

This work demonstrated the low-temperature control of the oxidation of Amorphous InGaZnOx (a-IGZO) films using inductively coupled plasma as a means of precisely tuning the properties of thin film transistors (TFTs) and as an alternative to post-deposition annealing at high temperatures. The effects of the plasma treatment of the as-deposited a-IGZO films were investigated by assessing the electrical properties of TFTs incorporating these films. A TFT fabricated using an a-IGZO film exposed to an Ar-H2-O2 plasma at substrate temperatures as low as 300 °C exhibited the best performance, with a field effect mobility as high as 42.2 cm2 V−1 s−1, a subthreshold gate voltage swing of 1.2 V decade−1, and a threshold voltage of 2.8 V. The improved transfer characteristics of TFTs fabricated with a-IGZO thin films treated using an Ar-H2-O2 plasma are attributed to the termination of oxygen vacancies around Ga and Zn atoms by OH radicals in the gas phase.

Variability Study for Low-Voltage Microelectromechanical Relay Operation

Body-biased microelectromechanical relays previously have been developed for ultralow-power digital logic applications and demonstrated to reliably switch ON/OFF with sub-50-mV gate voltage swing. Since variability in relay switching voltages can practically limit reduction in the operating voltage of a relay-based integrated circuit, the effects of process-induced variations and device operating conditions, as well as the stability of relay switching voltages, are investigated in this paper. Antistiction coating is shown to stably reduce hysteresis voltage and random variation thereof, which is beneficial for voltage scaling.

Mobility overestimation due to minority carrier injection and trapping in organic field-effect transistors

Abstract Donor–acceptor (D–A) polymers are promising candidates as semiconductors in flexible transistors because of their high mobility. However, in recent studies on D–A polymer transistors, device characteristics deviate from the idealized transistor model, which is commonly used for extracting mobility, and show an abrupt turn-on in the drain current when measured as a function of gate voltage. To examine the validity of the reported mobility values of D–A polymers, we investigate the detailed mechanism of the nonideal electrical characteristics by device simulation based on a split-channel model, where the gate voltage swing on the drain side is higher than that on the source side. We demonstrate that minority carriers injected into low-bandgap D–A polymers (electrons in the case of usual D–A polymers) at high drain voltages and low gate voltages cause insufficient pinch off, resulting in an overestimation of mobility if the conventional mobility extraction method is used. A more reliable method for estimating mobility from the nonideal transfer characteristics is developed and applied to recent reports. It was determined that the mobility values of D–A polymers in the recent reports were overestimated by a factor of 1.7–94 or more.

High-Performance LPCVD-SiNx/InAlGaN/GaN MIS-HEMTs With 850-V 0.98-$\text{m}{\Omega} \cdot$ cm2 for Power Device Applications

We demonstrate the electrical performances of the quaternary InAlGaN/GaN MIS-HEMTs with high quality SiNx gate dielectric and surface passivation layer deposited by low pressure chemical vapor deposition (LPCVD) at 780.C. Excellent LPCVD-SiNx/InAlGaN interface and SiNx film quality were obtained, resulting in very high output current density, a very small threshold voltage hysteresis and steep subthreshold slope. The LPCVD-SiNx/InAlGaN/GaN MIS-HEMT device exhibited high on/off current ratio, large gate voltage swing, high breakdown voltage, and very low dynamic on-resistance (RON) degradation, meaning effective current collapse suppression compared to the plasma enhanced chemical vapor deposition -SiNx/InAlGaN/GaN MIS-HEMTs. The corresponding specific on-resistance (RON,sp) for LPCVD-SiNx device was as low as 0.98 mEcm2, yielding a high figure of merit of 737 MW/cm2. These results demonstrate a great potential of the LPCVD-SiNx/InAlGaN/GaN MIS-HEMTs for high-power switching applications.

Static negative capacitance of a ferroelectric nano-domain nucleus

Miniaturization of conventional field effect transistors (FETs) approaches the fundamental limits beyond which opening and closing the transistor channel require higher gate voltage swing and cause higher power dissipation and heating. This problem could be eliminated by placing a ferroelectric layer between the FET gate electrode and the channel, which effectively amplifies the gate voltage. The original idea of using a bulk ferroelectric negative capacitor suffers however from irreversible multi-domain ferroelectric switching, which does not allow us to stabilize static negative capacitance, while a recent reversible solution with super-lattices may be difficult to integrate onto FET. Here, we introduce a solution which provides static negative capacitance from a nano-domain nucleus. Phase-field simulations confirm the robustness of this concept, the conveniently achievable small effective negative capacitance and the potentially high compatibility of such a negative nano-capacitor with FET technology.

Homodyne phase sensitive terahertz spectrometer

We present the theory of a field effect transistor (FET) operating as a THz or far infrared detector. We demonstrate that the detected signal is enhanced by orders of magnitudes by using a homodyne detection scheme involving the interference of a weak incoming signal and a strong signal of a local oscillator with the close frequency. We developed a theory valid for the arbitrary relationship between the amplitude of the local oscillator and the gate voltage swing. Remarkably, the response saturates at a high local oscillator intensity at the value which depends on the phase difference between the signals. The observed gain in this regime is over 100, and the predicted maximum gain in this operating regime is on the order of 105. These results show that a FET could be used as a sensitive spectrometer and/or interferometer when exposed to a strong tunable local oscillator signal with the varying frequencies and phases. This regime of the detector operation is very promising for the interferometric and spectroscopic applications in the subterahertz and terahertz ranges.

GaN MOSHEMT employing HfO2 as a gate dielectric with partially etched barrier

In order to suppress the gate leakage current of a GaN high electron mobility transistor (GaN HEMT), a GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is proposed, in which a metal-oxide-semiconductor gate with high-dielectric-constant HfO2 as an insulating dielectric is employed to replace the traditional GaN HEMT Schottky gate. A 0.5 μm gate length GaN MOSHEMT was fabricated based on the proposed structure, the barrier layer is partially etched to produce a higher transconductance without deteriorating the transport characteristics of the two-dimensional electron gas in the channel, the gate dielectric is HfO2 deposited by atomic layer deposition. Current-voltage characteristics and radio frequency characteristics are obtained after device preparation, the maximum current density of the device is 900 mA mm−1, the source-drain breakdown voltage is 75 V, gate current is significantly suppressed and the forward gate voltage swing range is about ten times higher than traditional GaN HEMTs, the GaN MOSHEMT also demonstrates radio frequency characteristics comparable to traditional GaN HEMTs with the same gate length.

Highly gate-tuneable Rashba spin-orbit interaction in a gate-all-around InAs nanowire metal-oxide-semiconductor field-effect transistor

III-V semiconductors have been intensively studied with the goal of realizing metal-oxide-semiconductor field-effect transistors (MOSFETs) with high mobility, a high on-off ratio, and low power consumption as next-generation transistors designed to replace current Si technology. Of these semiconductors, a narrow band-gap semiconductor InAs has strong Rashba spin-orbit interaction, thus making it advantageous in terms of both high field-effect transistor (FET) performance and efficient spin control. Here we report a high-performance InAs nanowire MOSFET with a gate-all-around (GAA) structure, where we simultaneously control the spin precession using the Rashba interaction. Our FET has a high on-off ratio (104~106) and a high field-effect mobility (1200 cm2/Vs) and both values are comparable to those of previously reported nanowire FETs. Simultaneously, GAA geometry combined with high- κ dielectric enables the creation of a large and uniform coaxial electric field (>107 V/m), thereby achieving highly controllable Rashba coupling (1 × 10−11 eVm within a gate-voltage swing of 1 V), i.e. an operation voltage one order of magnitude smaller than those of back-gated nanowire MOSFETs. Our demonstration of high FET performance and spin controllability offers a new way of realizing low-power consumption nanoscale spin MOSFETs.

Comparative studies of normally-off Al0.26Ga0.74N/AlN/GaN/Si high electron mobility transistors with different gate structures

Systematic designs to achieve normally-off operation and improved device performance for Al0.26Ga0.74N/AlN/GaN high electron mobility transistors (HEMTs) grown on a Si substrate are investigated in this work. The step-by-step approach includes: (1) devising a thin AlGaN/AlN composite barrier, (2) introducing fluoride ions within the active region by using CF4 plasma treatment, (3) growing the Al2O3 oxide passivation layers within gate-drain/source regions by using a cost-effective ozone water oxidization technique, and (4) integrating a metal-oxide-semiconductor gate (MOS-gate) design with high-k Al2O3 gate dielectric. Devices with four different evolutionary gate structures have been compared and studied. Variations of threshold voltage (Vth), Hooge coefficients (αH), maximum drain-source current density (IDS, max), maximum extrinsic transconductance (gm, max), gate-voltage swing (GVS) linearity, two-terminal gate-drain breakdown/turn-on voltages (BVGD/Von), on/off current ratio (Ion/Ioff), and high-temperature characteristics up to 450K are also investigated.

Comparative studies on AlGaN/GaN/Si MOS-HFETs with Al2O3/TiO2 stacked dielectrics by using an ultrasonic spray pyrolysis deposition technique

Al0.26Ga0.74N/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) grown on a Si substrate with Al2O3/TiO2 stacked gate dielectrics formed by using non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique are investigated. High permittivity (k) values of Al2O3 and TiO2 were characterized to be 9 and 46.1, respectively, with an equal layer thickness of 10 nm. The present MOS-HFET (Schottky-gate HFET) design has demonstrated enhanced device characteristics at 300 K, including maximum drain–source current density (IDS,max) of 725 (530) mA/mm, IDS at VGS = 0 V (IDSS0) of 471 (383) mA/mm, gate-voltage swing (GVS) of 2.5 (1.6) V, two-terminal gate-drain breakdown voltage (BVGD) of −182 (−121) V, turn-on voltage (Von) of 4.9 (3.2) V, three-terminal off-state drain-source breakdown voltage (BVDS) of 174 (103) V, on/off current ratio (Ion/Ioff) of 5.6 × 107 (3.7 × 103), unity-gain cut-off frequency (fT) of 10.3 (6.8) GHz, maximum oscillation frequency (fmax) of 14.8 (8.6) GHz, and power-added efficiency (P.A.E.) of 38.5% (31.7%) at 2.4 GHz. High temperature device characteristics up to 450 K are also discussed.

Simulation of Deep-Level Trap Distributions in AlGaN/GaN HEMTs and Its Influence on Transient Analysis of Drain Current

AlGaN/GaN high electron mobility transistors for high efficiency power switching applications are susceptible to charge trapping by deep-levels in the GaN buffer resulting in current collapse during gate and drain voltage swings. Although drain-current transient based methodologies have been used consistently to extract trap parameters, the factors affecting the non-exponential nature of the transient are still not well understood. No effort at accurately replicating multiple deep-levels in the GaN buffer to simulate transient response of GaN based power devices has been reported previously. In this work, we present numerical simulation results of HEMTs having multiple discrete trap states as well as band-like distribution of traps in the GaN band-gap. On-state current of synchronous gate and drain pulsing simulations show current as a sum of stretched multiexponentials, with stretching factor showing trap and Fermi-level dependence. Using this capability incorporated into FLOODS TCAD simulator and definition of deep-levels in the GaN buffer precisely, modeling of non-exponential transients and associated wide peaks in the transient derivatives can be carried out accurately.

Abrupt current switching in graphene bilayer tunnel transistors enabled by van Hove singularities.

In a continuous search for the energy-efficient electronic switches, a great attention is focused on tunnel field-effect transistors (TFETs) demonstrating an abrupt dependence of the source-drain current on the gate voltage. Among all TFETs, those based on one-dimensional (1D) semiconductors exhibit the steepest current switching due to the singular density of states near the band edges, though the current in 1D structures is pretty low. In this paper, we propose a TFET based on 2D graphene bilayer which demonstrates a record steep subthreshold slope enabled by van Hove singularities in the density of states near the edges of conduction and valence bands. Our simulations show the accessibility of 3.5 × 104 ON/OFF current ratio with 150 mV gate voltage swing, and a maximum subthreshold slope of (20 μV/dec)−1 just above the threshold. The high ON-state current of 0.8 mA/μm is enabled by a narrow (~0.3 eV) extrinsic band gap, while the smallness of the leakage current is due to an all-electrical doping of the source and drain contacts which suppresses the band tailing and trap-assisted tunneling.

Investigations on MgO-dielectric GaN/AlGaN/GaN MOS-HEMTs by using an ultrasonic spray pyrolysis deposition technique

This work investigates GaN/Al0.24Ga0.76N/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) grown on a Si substrate with MgO gate dielectric by using the non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. The oxide layer thickness is tuned to be 30 nm with the dielectric constant of 8.8. Electron spectroscopy for chemical analysis (ESCA), secondary ion mass spectrometry (SIMS), atomic force microscopy (AFM), transmission electron microscopy (TEM), C–V, low-frequency noise spectra, and pulsed I–V measurements are performed to characterize the interface and oxide quality for the MOS-gate structure. Improved device performances have been successfully achieved for the present MOS-HEMT (Schottky-gate HEMT) design, consisting of a maximum drain-source current density (IDS, max) of 681 (500) mA/mm at VGS = 4 (2) V, IDS at VGS = 0 V (IDSS0) of 329 (289) mA/mm, gate-voltage swing (GVS) of 2.2 (1.6) V, two-terminal gate-drain breakdown voltage (BVGD) of −123 (−104) V, turn-on voltage (Von) of 1.7 (0.8) V, three-terminal off-state drain-source breakdown voltage (BVDS) of 119 (96) V, and on/off current ratio (Ion/Ioff) of 2.5 × 108 (1.2 × 103) at 300 K. Improved high-frequency and power performances are also achieved in the present MOS-HEMT design.

Microsecond Crystallization of Amorphous Silicon Films on Glass Substrates by Joule Heating

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films was conducted by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. The phase-transformation phenomena during the JIC process were detected electrically and optically by the in-situ measurements of input voltage/current and normal reflectance at wavelength of 532 nm. We devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. JIC-processed poly-Si thin-film transistors were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs. The p-channel JIC poly-Si TFT with W/L = 7 μm/7 μm exhibited a field effect mobility of 38.9 cm2/V-s, a threshold voltage of −2.8 V, and a gate voltage swing of 0.35 V/dec.