Gate Voltage Swing Research Articles

Characteristics of Liquid-Phase-Deposited SrTiO3 Films on GaN and AlGaN/GaN Wafer

Through a simple, low-temperature liquid-phase deposition (LPD) method, SrTiO3 thin films were deposited on GaN as the gate dielectric for metal oxide semiconductor high electron mobility transistor application. X-ray photoelectron spectroscopy was employed to characterize the films. Electrical characteristics of the SrTiO3 films on GaN showed that the lowest leakage current was 4.2x10-9 A/cm2 at -1 MV/cm after annealing at 400°C. AlGaN/GaN MOSHEMTs with LPD-SrTiO3 of 20 nm-thick as the gate dielectric were also fabricated. The suppressed gate leakage current improves both subthreshold slope and on/off current ratio. Wider gate voltage swing and flatter transconductance of the MOSHEMT demonstrate better device linearity.

Near Room-Temperature Liquid-Phase Deposition of Barium-Doped TiO2 on n-GaN and its Application to AlGaN/GaN MOSHEMTs

Barium-doped TiO2 films deposited on GaN layers at low temperature through a simple liquid-phase deposition method is investigated. The use as a gate dielectric in AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs) is also demonstrated. The electrical characteristics of the metal-oxide-semiconductor (MOS) structure on n-doped GaN show that the leakage current density is about 5.09 × 10-9 A/cm2 at 1 MV/cm, and the breakdown field is more than 13 MV/cm. The maximum drain current density of the AlGaN/GaN MOSHEMTs is higher than that of HEMTs, in which a wider gate voltage swing, a lower sub-threshold swing (112mV/dec), and a higher ION/IOFF ratio (4.5×105) are obtained.

Self-Aligned Coplanar a-IGZO TFTs and Application to High-Speed Circuits

We report a self-aligned coplanar amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) using an a-IGZO/SiO2 stack layer. From the channel-length dependence of the total resistance for the TFTs, the channel and parasitic resistances were found to be 8.4 kΩ/μm and 9.7 kΩ/sq, respectively. The fabricated a-IGZO TFT exhibits field-effect mobility of 23.3 cm2/V ·s, threshold voltage of 3.6 V, and gate voltage swing of 203 mV/dec. A 23-stage ring oscillator made of the self-aligned TFTs exhibits a propagation delay time of 17 ns/stage at a supply voltage of 22 V.

Investigation on the Doping Dependence of Solution-Processed Zinc Tin Oxide Thin Film and Thin-Film Transistors

The effect of the tin (Sn) concentration in zinc tin oxide (ZTO) films fabricated using a spin-coating process and its effect on ZTO channel thin film transistors (TFTs) with various Sn concentrations were examined. Spin-coated ZTO films with various Sn concentrations were nanocrystalline and had high transmittance (>85%) in the visible region. As the Sn concentration increased, the carrier concentration and resistivity of the nanocrystalline ZTO (nc-ZTO) films ranged from 9.6 × 1014 cm−3 to 2.2 × 1016 cm−3 and from 1.5 × 103 Ω-cm to 1.6 × 102 Ω-cm, respectively. The nc-ZTO channel TFTs that were deposited as a function of Sn and Zn concentrations exhibited a subthreshold gate voltage swing (S) of 1.1–1.2 V decade−1, an on/off ratio of 105–106, a threshold voltage (Vth) of -0.8–1.7 V, and a μFE value of 2.4–2.6 cm2 V−1 s−1. The threshold voltage shift toward the negative gate bias as the Sn concentration in the nc-ZTO TFTs increased indicates the existence of sufficient charge carriers needed to form conductive channels.

Comparative investigation of InGaP/GaAs pseudomorphic field-effect transistors with triple doped-channel profiles

In this article, the comparison of DC performance on InGaP/GaAs pseudomorphic field-effect transistors with tripe doped-channel profiles is demonstrated. As compared to the uniform and high-medium-low doped-channel devices, the low-medium-high doped-channel device exhibits the broadest gate voltage swing and the best device linearity because more twodimensional electron gases are formed in the heaviest doped channel to enhance the magnitude of negative threshold voltage. Experimentally, the transconductance within 50% of its maximum value for gate voltage swing is 4.62 V in the low-medium-high doped-channel device, which is greater than 3.58 (3.30) V in the uniform (high-medium-low) doped-channel device.

Inclusion of the Accumulation Region in the Compact Models of Bulk and SOI FinFETs

TCAD simulations show the difference in the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input-voltage equation valid in all regions of operation is proposed for double-gate FinFETs with intrinsic or lightly doped bodies. This results in a surface-potential-based compact model of FinFETs, which is valid in all regions of operation and is verified by comparison with TCAD simulations.

High-Performance Amorphous Indium–Gallium–Zinc–Oxide Thin-Film Transistor With a Self-Aligned Etch Stopper Patterned by Back-Side UV Exposure

We report the fabrication of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with a bottom-gate inverted-staggered structure with an etch stopper formed by a self-aligned process using back-side UV exposure. In addition to reduction in process complexity, the gate-to-source capacitance of an a-IGZO TFT is significantly reduced, resulting in fast TFT circuits. The fabricated TFT exhibits a field-effect mobility value of 42.59 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s , a threshold voltage of 6.1 V, and a gate voltage swing of 374 mV/dec. An 11-stage ring oscillator made of TFTs shows a propagation delay time of 56 ns/stage at 25 V.

High-performance ZnO thin-film transistor fabricated by atomic layer deposition

We report the fabrication and characteristics of a ZnO thin-film transistor (TFT) using a 50 nm thick ZnO film as an active layer on an Al2O3 gate dielectric film deposited by atomic layer deposition. Lowering the deposition temperature allowed the control of the carrier concentration of the active channel layer (ZnO film) in the TFT device. The ZnO TFT fabricated at 110 °C exhibited high-performance TFT characteristics including a saturation field-effect mobility of 11.86 cm2 V−1 s−1, an on-to-off current ratio of 3.09 × 107 and a sub-threshold gate-voltage swing of 0.72 V decade−1.

Reduction of Hot Carrier Effects in Silicon-on-Glass TFTs

Hot carrier (HC) instability of thin-film transistors (TFTs) fabricated on single-crystal,silicon-on-glass (SiOG) substrates is studied. The formation of the SiOG substrate is achieved by the transfer of a single-crystal silicon film to a display-glass substrate. The transfer process creates an in-situ barrier layer free of mobile ions in the glass adjacent the silicon film. The n- and p-channel TFT transfer characteristics typically exhibit excellent on-state performance with gate voltage swing values of 180 mV/decade, electron and hole mobilities of ∼ 251 and 201 cm2/V·s respectively, and threshold voltages of approximately −0.3 and −1.2 V for the n- and p-channel TFT’s respectively. While p-channel TFTs exhibit good stability, on-current degradation is observed in the transfer characteristics of the n-channel TFT. The degradation is due to HC stress. In this study, the integration of a lightly doped drain (LDD) structure in the n-channel SiOG TFTs to minimize HC instability is reported. The LDD design incorporates 2 μm offset regions. The offset regions are lightly doped (n-) with phosphorus ions implanted at 10 keV. N-levels of ∼ 1 × 1013, 2 × 1013, and 3 × 1013 cm−2 are analyzed to determine the optimum doping conditions that reduce HC instability while minimizing degradation in the on-state device performance.

A low-voltage, low power divide-by-4 LC-tank injection-locked frequency divider

A low-voltage wide locking range injection-locked frequency divider (ILFD) using a standard 0.18 µm complementary metal-oxide-semiconductor process is presented. The ILFD is based on a differential LC VCO with one injection metal oxide semiconductor field effect transistor (MOSFET) for coupling external signals to the resonator. The low-voltage operation and wide locking range is obtained by boosting the gate voltage swing of the ILFD. Measurements show that at the supply voltage of 0.67 V, the divider's free-running frequency is tunable from 3.91 to 4.22 GHz, and the core power consumption is 1.87 mW. At the incident power of 0 dBm the divide-by-4 operation range is about 2 GHz (12.3%), from the incident frequency 15.3–17.3 GHz. The divide-by-2 locking range is about 5.1 GHz (77%), from the incident frequency 4.1–9.2 GHz.

Electrical characteristics of Si MFIS-FETs using P(VDF-TrFE) thin films

Ferroelectric polymer memory transistors were fabricated by using PMMA (poly methyl metacrylate)-blended P(VDF-TrFE) (polyvinyliden fluoride-trifluoroethylene) as the gate ferroelectric film. The film was spin-coated on an SiO 2-coated n-type Si wafer with the p-type source and drain regions and Au electrodes for the source, drain, and gate terminals were formed by thermal evaporation, followed by wet chemical etching. The on/off ratio and memory window width of the fabricated ferroelectric-gate FET were typically 10 7 and 5 V at the gate voltage swing of ±11 V, respectively. As for the data retention characteristics, the current on/off ratio of approximately 10 3 was obtained at 10 3 s after write operation.

Enhanced performance of a-IGZO thin-film transistors by forming AZO/IGZO heterojunction source/drain contacts

A low-cost Al-doped ZnO (AZO) thin film was deposited by radio-frequency magnetron sputtering with different Ar/O2 flow ratios. The optical and electrical properties of an AZO film were investigated. A highly conductive AZO film was inserted between the amorphous InGaZnO (a-IGZO) channel and the metal Al electrode to form a heterojunction source/drain contact, and bottom-gate amorphous a-IGZO thin-film transistors (TFTs) with a high κ HfON gate dielectric were fabricated. The AZO film reduced the source/drain contact resistivity down to 79 Ω cm. Enhanced device performance of a-IGZO TFT with Al/AZO bi-layer S/D electrodes (W/L = 500/40 µm) was achieved with a saturation mobility of 13.7 cm2 V−1 s−1, a threshold voltage of 0.6 V, an on-off current ratio of 4.7 × 106, and a subthreshold gate voltage swing of 0.25 V dec−1. It demonstrated the potential application of the AZO film as a promising S/D contact material for the fabrication of the high performance TFTs.

Highly stable amorphous indium–gallium–zinc-oxide thin-film transistor using an etch-stopper and a via-hole structure

Highly stable amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etch-stopper and via-hole structure. The TFTs exhibited 40 cm2/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (Δ V th) at room temperature. The excellent stability is attributed to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at 60°C showed that there was a smaller Δ V th in the AC stress compared with the DC stress for the same effective stress time, indicating that the trapping of the carriers at the active layer–gate insulator interface was the dominant degradation mechanism.

A Novel Transparent AZO-Gated $\hbox{Al}_{0.2} \hbox{Ga}_{0.8}\hbox{As/In}_{0.2}\hbox{Ga}_{0.8}\hbox{As}$ pHEMT and Photosensing Characteristics Thereof

A novel transparent Al-doped ZnO (AZO)-gated Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> As pseudomorphic high-electron mobility transistor (pHEMT) has been comprehensively investigated. The proposed AZO-gated pHEMT has demonstrated superior temperature-dependent performance, including two-terminal gate-drain breakdown/turn-on voltages of - 63/3.4 (-56.4/3.4) V, an intrinsic voltage gain A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> of 257 (176), and a gate voltage swing of 1.18 (1.13) V at 300 (450) K. An excellent thermal threshold coefficient ∂V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> /ΘT of -1.8 mV/K was also obtained. A conventional Au-gated device with the same gate dimensions of 1 × 100 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was also fabricated in comparison. In addition, high optical transmittance values of 82%-98% for incident energy values of 1.24-3.54 eV are achieved in the AZO film. The present AZO-gated HEMT has demonstrated three-terminal tunable optical responsivity due to a photovoltaic effect. Photosensing characteristics under different radiation wavelengths of white light, red light (632 nm), and near infrared (980 nm) are also studied.

Stability Diagrams of Triple-Dot Single-Electron Device with Single Common Gate

Triple-dot single-electron devices with a single common gate have been studied. The overall stability diagram of the single-electron device with a homogeneous tunnel capacitance Cj and a homogeneous gate capacitance Cg is derived algebraically. If the set of excess electron numbers in the three islands (n1, n2, n3) is (n, n, n), (n, n + 1, n), or (n, n - 1, n), where n is an arbitrary integer, the corresponding stability region S(n1, n2, n3) exists for any Cg/Cj. S(n, n, n), S(n, n + 1, n), and S(n, n - 1, n) for all n are arranged along the Vg axis in the order of n1 + n2 + n3, where Vg is gate voltage, and neighboring stability regions overlap for any Cg/Cj ratio. Overlaps between S(n, n, n) and S(n, n ±1, n) for all n have identical kite-like shapes. Overlaps between S(n, n + 1, n) and S(n + 1, n, n + 1) for all n have identical rhombus shapes. Turnstile operations are possible by alternating gate voltage around overlaps between S(n, n, n) and S(n, n ±1, n) and around overlaps between S(n, n + 1, n) and S(n + 1, n, n + 1), though the sequences of single-electron transfers are different. The range of drain voltage and the swing of gate voltage for turnstile operation are estimated. The overlap between S(n, n + 1, n) and S(n + 1, n, n + 1) seems superior to the overlap between S(n, n, n) and S(n, n ±1, n) because of the larger ratio of the drain voltage range to the gate voltage swing, though the overlap between S(n, n + 1, n) and S(n + 1, n, n + 1) might require higher reliability against the nonuniformity of gate capacitances.

Transparent Flexible Circuits Based on Amorphous-Indium–Gallium–Zinc–Oxide Thin-Film Transistors

Circuits implemented with high-performance amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) are realized on polyimide/polyethylene-terephthalate plastic substrates. The TFTs on plastic exhibit a saturation mobility of 19 cm2/V·s and a gate voltage swing of ~0.14 V/dec. For an input of 20 V, an 11-stage ring oscillator operates at 94.8 kHz with a propagation delay time of 0.48 μs. A shift register, consisting of ten TFTs and one capacitor, operates well with good bias stability. AC driving of pull-down TFTs gives the gate driver an improved lifetime of over ten years.

Low Voltage-Driven CMOS Circuits Based on SiOG

The fabrication of the low voltage-driven inverter, ring oscillator, and shift resistor using n- and p-channel thin-film transistors (TFTs) based on the silicon-on-glass (SiOG) substrate was studied. The manufacturing process of n- and p-channel TFTs was the same as that of low temperature poly-Si. The field-effect mobilities of n- and p-channel TFTs fabricated in SiOG are 226 and , respectively. The TFTs exhibited a symmetric threshold voltage of and a gate voltage swing of . The total propagation delay time of the complementary metal oxide semiconductor (CMOS) inverter was at a supply voltage of . In addition, the rise and fall times of the shift register were found to be 0.5 and at a of , respectively.

High-Performance a-IGZO Thin-Film Transistor Using $ \hbox{Ta}_{2}\hbox{O}_{5}$ Gate Dielectric

In this letter, we report the fabrication of an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor with a high-k dielectric layer on a glass substrate. The room-temperature-deposited a-IGZO channel with Ta2O5 exhibits the following operating characteristics: a threshold voltage of 0.25 V, a drain-source current on/off ratio of 105, a subthreshold gate voltage swing of 0.61 V/decade, and a high field-effect mobility of 61.5 cm2/V·s; these characteristics make it suitable for use as a switching transistor and in low-power applications.

Gate voltage swing enhancement of InGaP/InGaAs pseudomorphic HFET with low-to-high double doping channels

Direct current characteristics of an InGaP/InGaAs pseudomorphic HFET employing low-to-high double doping channels are first demonstrated and compared with the conventional single doping-channel device. Because the lower InGaAs channel is heavily doped and two-dimensional electron gas is formed in this channel, the threshold voltage is extended to −3.7 V. Experimentally, the transconductance within 50% of its maximum value for gate voltage swing up to 4.5 V is achieved in the studied device, which is greater than that of 3.85 V in the single doping-channel device.

Low Voltage Driven CMOS Circuits Based on Silicon on Glass

Low voltage driven inverter, ring oscillator and shift resistor using n- and p- channel TFTs based on Corning® silicon-on-glass substrates (SiOG) is studied. The field effect mobility of n- and p-channel TFTs based on SiOG are 226 cm2/V s and 165 cm2/V, respectively. TFTs exhibit the symmetric threshold voltage of ± 1.1 V and gate voltage swing of 0.21 ~ 0.23 V/dec. The total propagation delay time of the CMOS inverter is 2.54ns at the supply voltage of 7 V. In addition, the rise and fall times of the shift register are found to be 0.5 µs and 0.7 µs at VDD of 7 V, respectively. Therefore, high performance integrated circuits can be possible on SiOG using CMOS technologies.