Gate Underlap Region Research Articles

Performance Optimization of Monolayer 1T/1T’-2H MoX2 Lateral Heterojunction Transistors

Recently, 2-D transition metal dichalcogenides (TMDs) lateral heterojunction field-effect transistors (FETs) have been demonstrated experimentally, in which metallic TMDs were used for the source/drain. In this work, we systematically investigate the contact property and device performance of monolayer 1T/1T $^{\prime }$ -2H MoS2, MoSe2, and MoTe2 FETs. Schottky barrier (SB) heights are extracted from density functional theory calculations, and nonequilibrium Green’s function transport simulations have been performed to study device characteristics. Our simulation results show that the inherent SB strongly affects the overall performance of these devices. Here, we optimize the performance of TMD lateral heterojunction FETs by using two different approaches. First, we have improved the electrostatic control by scaling equivalent oxide thickness and gate underlap, which boosts both ON- and OFF-state characteristics, making the device suitable for high-performance applications. On the other hand, moderate doping has been used in the gate underlap region, improving ON/OFF current ratio with negligible impacts on ON-state characteristics, and this approach is more preferred for low-power applications. This study reveals that 1T $^{\prime }$ -2H MoTe2 FET shows the highest ON current ( $\sim 1$ mA/ $\mu \text{m}$ ) among the three with a reasonably small subthreshold swing (80 mV/dec) if properly scaled, while 1T-2H MoS2 FET exhibits the highest ${I} _{\scriptscriptstyle{\text{ON}}}/{I} _{\scriptscriptstyle{\text{OFF}}}$ (~107) when ohmic contact is established with moderate doping in the gate underlap region. This study not only provides physical insight into the electronic devices based on novel TMD heterostructures but also suggests engineering practice for device performance optimization in experiments.

Analytical modeling analysis and simulation study of dual material gate underlap dopingless TFET

An analytical model of dual material single gate doping-less Tunnel FET (DM-GU-TFET) with gate underlap regions has been proposed. The potential of gate underlap area with channel area has been examined using modeling and the results are validated using TCAD simulation at boundary conditions. The proposed structure has been divided into ten distinct sections (counting source/drain depleted sections) to get potential models while settling the 1-Dimensional and 2-Dimensional Poisson equations (PE) condition in the respective sections. To settle the PE's at different limit conditions, explanatory estimate strategy is proposed and tested. The effect of geometric morphology, for instance under-lap length, has been analyzed, which is dependent on electrical attributes of DM-GU-TFET. The parabolic approximation technique is used to settle the PE's at various interface conditions. The effect of structural variations viz. gate underlap length and tunneling length is scrutinized using electrical characteristics of DM-GU-TFET. The resultant characteristics of proposed dopingless TFET represent a noteworthy improvement in surface potentials with variation in length of spacer region, underlap section and tunneling region.

An analytical modeling of charge plasma based Tunnel Field Effect Transistor with impacts of gate underlap region

Abstract In this manuscript, a compact model of source depletion, drain depletion and channel potential in the charge plasma based Tunnel Field Effect Transistor (U-CPBTFET) with two underlap regions (source-gate and gate-drain) is proposed and developed. The shift in potential due to variation in length of gate underlap regions has been studied and authenticated with TCAD simulation results by operating proposed device in various biasing condition. The surface potential model is derived by splitting the silicon substrate into seven different regions (including source and drain depleted regions) and resolving the pseudo-2-D Poisson's equation (PE) in the above mentioned locales. Parabolic approximation method is applied to solve the PEs at different boundary conditions. The impact of parametric variation such as spacer length and channel material has been investigated on the basis of electrical attributes of U-CPBTFET.

Parametric Variation Analysis of Symmetric Double Gate Charge Plasma JLTFET for Biosensor Application

Nanoscale devices have great potential for providing a platform for detecting biomolecules. There are a number of difficulties observed during the fabrication process of these devices, such as random dopant fluctuation, thermal budget, and so on. To cut down these problems, charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field-effect transistor (CPB DM-JLTFET) for the label free electrical recognition of biomolecules like cell, enzyme, deoxyribonucleic acid, protein, and so on via incorporating the dielectric modulation technique. A gate underlap region is formed in the device via etching oxide material. Label free detection of biomolecules depends upon the electrical property of biomolecules. The effect of device parameters such as cavity length and cavity thickness on surface potential, subthreshold slope, $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ ratio, and their sensitivity have been discussed. This paper investigates the performance of CPB DM-JLTFET for biomolecule sensing applications while varying dielectric constant, surface density, cavity length, and cavity thickness at different biasing conditions. The device proposed is implemented and simulated by using an ATLAS device simulator.

Analytical modeling of split-gate junction-less transistor for a biosensor application

This paper represents the analytical modeling of split-gate Dielectric Modulated Junction Less Transistor (JLT) for label free electrical detection of bio molecules. Some part of the channel region is opened for providing the binding sites for the bio molecules unlike conventional MOSFET which is enclosed with the gate electrode. Due to this open area, the surface potential of this region affected by the charged and neutral bio molecules immobilized to the open region of channel. Surface potential of the channel region obtained by solving two-Dimensional Poisson's equation by potential profile having parabolic nature through channel region using technique called conformal mapping. By deriving the surface potential model, derivation of threshold model can also be done. For the detection of bio molecule, variation in to the threshold voltage due to binding of bio molecule in the gate underlap region is the sensing metric.

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.

Underlapped FinFET on insulator: Quasi3D analytical model

The work presented in this paper analyse the influence of gate underlap region (present either near the source end or near the drain end) on the performance of FinFET using an efficient quasi 3D analytical model carried out by using separation of variable technique. Various parameters analysed in this work are: surface potential, electric field, threshold voltage (Vth), Subthreshold slope (SS), Drain Induced Barrier Lowering (DIBL) and sub-threshold drain current for different channel and underlap length. Analytical results obtained from the developed model are validated by 3-D ATLAS device simulation software results. Analog and RF performance metrics are also extracted for different lengths of underlap region and compared with the conventional FinFET through extensive device simulation. The influence of the back gate voltage on the electrostatics of the underlap FinFET is also investigated. The single stage common source amplifier using conventional and underlap FinFET has also been analysed. Apart from this, switching speed of the device is also investigated by comparing Ion/Ioff ratio and delay for different underlap and channel length.

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

ABSTRACTIn this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.

Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve Ion. We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si3N4 spacers, with kappa=20 spacers, we show that it is possible to achieve an 80% increase in Ion at iso-Ioff conditions and a 15% decrease in the inverter delay for a fan-out of four.