Underlapped FinFET on insulator: Quasi3D analytical model

Abstract

The work presented in this paper analyse the influence of gate underlap region (present either near the source end or near the drain end) on the performance of FinFET using an efficient quasi 3D analytical model carried out by using separation of variable technique. Various parameters analysed in this work are: surface potential, electric field, threshold voltage (Vth), Subthreshold slope (SS), Drain Induced Barrier Lowering (DIBL) and sub-threshold drain current for different channel and underlap length. Analytical results obtained from the developed model are validated by 3-D ATLAS device simulation software results. Analog and RF performance metrics are also extracted for different lengths of underlap region and compared with the conventional FinFET through extensive device simulation. The influence of the back gate voltage on the electrostatics of the underlap FinFET is also investigated. The single stage common source amplifier using conventional and underlap FinFET has also been analysed. Apart from this, switching speed of the device is also investigated by comparing Ion/Ioff ratio and delay for different underlap and channel length.