Abstract
Abstract In this manuscript, a compact model of source depletion, drain depletion and channel potential in the charge plasma based Tunnel Field Effect Transistor (U-CPBTFET) with two underlap regions (source-gate and gate-drain) is proposed and developed. The shift in potential due to variation in length of gate underlap regions has been studied and authenticated with TCAD simulation results by operating proposed device in various biasing condition. The surface potential model is derived by splitting the silicon substrate into seven different regions (including source and drain depleted regions) and resolving the pseudo-2-D Poisson's equation (PE) in the above mentioned locales. Parabolic approximation method is applied to solve the PEs at different boundary conditions. The impact of parametric variation such as spacer length and channel material has been investigated on the basis of electrical attributes of U-CPBTFET.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
