An analytical modeling of charge plasma based Tunnel Field Effect Transistor with impacts of gate underlap region

Abstract

Abstract In this manuscript, a compact model of source depletion, drain depletion and channel potential in the charge plasma based Tunnel Field Effect Transistor (U-CPBTFET) with two underlap regions (source-gate and gate-drain) is proposed and developed. The shift in potential due to variation in length of gate underlap regions has been studied and authenticated with TCAD simulation results by operating proposed device in various biasing condition. The surface potential model is derived by splitting the silicon substrate into seven different regions (including source and drain depleted regions) and resolving the pseudo-2-D Poisson's equation (PE) in the above mentioned locales. Parabolic approximation method is applied to solve the PEs at different boundary conditions. The impact of parametric variation such as spacer length and channel material has been investigated on the basis of electrical attributes of U-CPBTFET.