Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

Abstract

The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve Ion. We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si3N4 spacers, with kappa=20 spacers, we show that it is possible to achieve an 80% increase in Ion at iso-Ioff conditions and a 15% decrease in the inverter delay for a fan-out of four.