Gate Turn-off Thyristor Research Articles

Advanced methods for diagnostics of the GTO thyristor

This paper gives an overview of diagnostic methods for the characterization of inhomogeneities of parameters of GTO segments, and their behaviour under static and dynamic conditions. In addition to measuring the forward voltage drop, OCVD lifetime and breakdown voltage of the cathode junction, the paper describes the measurement of small-signal current gains applied to the investigation of the inhomogeneities. Optical methods, such as the recombination radiation technique and the free-carrier absorption technique, are also discussed.

A New PWM Method of a Three-Level Inverter Considering Minimum Pulse Width and Neutral Voltage Balance Control.

A new PWM method of the three-level inverter using a digital signal processor, which is useful for large capacity instantaneous current controlled GTO inverters is presented.In case of the three-level inverter, short pulses are always necessary to output medium voltage vectors. The output waveform deteriorates from the ideal PWM waveform by the influence of the minimum pulse width limit of the GTO thyristors.In this PWM method, firstly, the switching sequences of voltage vectors which enable the neutral voltage balance control are selected.And then, from these sequences of voltage vectors, sequences which are not affected by the minimum pulse width limit of GTO are selected.Using these switching sequences, the voltage vector mean value control PWM method based on the space-vector control is proposed.

A study of turn-off limitations and failure mechanisms of GTO thyristors by means of 2-D time-resolved optical measurements

The failure mechanisms of Gate-Turn-Off (GTO) thyristors are investigated. Measurements based on a time-resolved free-carrier absorption (FCA) technique are used to support the presented models. The measurements serve to map the local carrier densities two-dimensionally, at any time of the switching cycle. Inductively loaded GTOs under snubberless operation are studied close to the safe-operating area (SOA) limit. Several important features of the destructive process are established. First, the existence of a quasi space-charge region, QSC, in the n base and charge focusing at the anode side of the device is noticed during the fall-time period. Secondly, a piling up of holes in the p base is followed by current filamentation during the tail period. The sequential behaviour of different phenomena and their possible causal explanations are also established. The expansion of the QSC towards the anode emitter causes the enhancement and focusing of the charge distribution in the vicinity of this junction. Two possible failure mechanisms, viz. local dynamic punch-through in the n base and local dynamic avalanche injection in the blocking junction are discussed in the light of the experimental results. It is also suggested that both the above mentioned failure mechanisms can be part of the chain of events leading to device failure. Regardless of which mechanism dominates, a high peak of excess holes appears in the p base in the beginning of the tail period. This charge debiases the cathode junction locally, i.e. compensates the negative bias of the cathode junction, and current filaments connecting the cathode and anode sides of the device are formed. The excessive power dissipation in the dominant filament causes failure and permanent damage.

The manufacture of silicon power devices using welding techniques

Epitaxial growth using chemical vapour deposition is the conventional manner for producing lightly doped silicon on more heavily doped substrates. With this technique it is difficult to achieve thick defect-free layers with high resistivity, and for interdigitated buried gate structure autodoping is a problem. A simpler and less expensive approach is the bonding together of two silicon wafers. The method employed is to polish the silicon surfaces to a roughness of less than 50 nm and to bring them together in a dust-free environment. In the present work, the wafers are cleaned, then washed and brought together in the wash bath to ensure minimum contamination. The bonded wafers are capable of withstanding all normal processing conditions, p-n diodes have been fabricated successfully with near ideal characteristics, and n-p-n bipolar transistors have been produced with the bonded interface in the p-base region. Whilst the density of recombination/generation centres at the bonded interface was around 5 × 10 11 cm −2 the average lifetime for minority carriers was 5 μs. By the addition of a p-type layer to the n-p-n transistors, gate turn-off thyristors have been produced successfully.

Continuous regulation of capacitive reactive power

A novel method for the continuous regulation of reactive power generated by a capacitor bank is presented. The two proposed control circuits consist of capacitor banks controlled by bidirectional switches which are built with antiparallel connected thyristor and GTO (gate turn-off thyristor) valves, or with two GTO valves. The current of the capacitor is regulated by turning off the GTO switch before zero current crossing. By tuning off the current, charge is trapped in the capacitor, resulting in a constant capacitor voltage. To avoid the current surge, the switch is turned on when the supply and capacitor voltage are equal. The current regulation is achieved by switching off the current for a part of each cycle. The feasibility of the method has been verified by extensive transient analysis. The advantage of the proposed system is the fast and continuous regulation of reactive power without inductance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new analytical model for gated turn-off of thyristors

A two-dimensional analytical model is developed to explain the storage phase of the turn-off mechanism in a gate turn-off thyristor. An expression is obtained from first principles for the position of the 'on' region plasma edge as a function of time, assuming a negative ramp for the gate current. The model contains no fitting parameters and addresses realistic issues such as high-injection effects, variation in the base transport factors, and the physical basis for the minimum 'on' region dimension. At the end of the storage time, the active injecting area of the cathode emitter reaches some minimum value which is calculated by imposing the condition that the supply of holes into the plasma region at that point of time is no longer sufficient for sustaining a flow of electrons across the p base. The model is used to investigate analytically the nature of variation of the storage time with anode current, rate of gate current ramp, and cathode island width. Experimental data are in excellent agreement with analytically predicted values. >

Performance limitations of a GTO with near-perfect technology

The performance of multiple-cell devices is limited by a redistribution of current during turn-off, caused by minor differences between the individual cells, which becomes important at high current density. A simple model, based on Gaussian statistics, is proposed where the degree of homogeneity between cells is expressed in terms of a technological quality factor k. It turns out that the increase of turn-off current for a gate turn-off thyristor (GTO) with a large number of cells is highly nonlinear. A major issue is the influence of the external load on the maximum turn-off current of a GTO. In the case of a typical inductive load, the turn-off capability of a device with a small number of segments n (n<100) hardly shows a difference between operation without and operation with a snubber. In contrast, for large GTOs (n>1000) snubberless operation imposes severe limitations on turn-off while a snubber with a realistic leakage inductance allows for a substantially larger turn-off current.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The utility requirements for a distribution fault current limiter

The need for a distribution current limiting device (DCLD) by the utility industry is addressed. An evaluation was made of what specifications would be acceptable and what DCLD technique would fill the utilities' needs. Using this survey and a distribution system analysis, a DCLD that could limit a 20 kA fault to 10 kA in a 15 kV circuit was shown to be the primary candidate for further development. The study showed that gate turn-off thyristors (GTOs) are the best technology available that could be developed into a practical DCLD. A recommendation was made to develop a DCLD using GTOs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Nonlinear capacitors in snubber circuits for GTO thyristors

Many applications with GTO thyristors require snubber circuits, at least for, turn-off. In achieving high switching frequencies there are conflicting design criteria for the snubber capacitor-losses versus timing conditions. Improvements to this situation are expected by employing nonlinear capacitors. Features of snubber circuits with nonlinear capacitors are described, and experimental results obtained from 50 A and 90 A GTO thyristors are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design considerations for p-i-n thyristor structures

An analysis of a high-voltage gate turn-off (GTO) thyristor structure with a double-layered n base (p-i-n structure) is presented. From integration of Poisson's equation, an expression for the forward-blocking voltage at the onset of avalanche breakdown is obtained. Simple design criteria are developed to calculate the optimal thickness and doping density of the n base of a conventional pnpn structure designed for a specific voltage-blocking capability. The same principle is applied to design for the doping densities and thicknesses of the high-resistivity region and the buffer layer of the p-i-n GTO structure. The forward-blocking voltage, as well as the on-state voltage (at a current density of 300 A cm/sup -2/) is predicted for a wide range of base layer thicknesses and doping densities to illustrate the available tradeoff options. Lowest on-state power dissipation for high blocking voltages (>6000 V) is predicted for a doping level of 5*10/sup 12/ cm/sup -3/ in the high-resistivity layer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparison of thyristor switched capacitor and voltage source GTO inverter type compensators for single phase feeders

The use of small static compensators for the control of voltage on single-phase distribution feeders is investigated. A candidate feeder system is examined to determine the size and type of reactive compensation required. A comparison is made of the single-phase design of a thyristor switched capacitor type compensator with an advanced gate turn-off thyristor voltage source inverter type of compensator. The advantages of the three-phase advanced compensator are not evident in the single-phase design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Operation of fluorescent lamps from batteries using pulsed power transistors and autotransformers

A robust transistor configuration is described for high-frequency pulse operation of fluorescent lighting, eliminating the need for clamping diode wastage of the turn-off spike energy, and facilitating the use of ferrite yoked autotransformers to couple the transistors to the lamps. Significant improvement in light output, for the same electrical power input, is gained by utilizing autotransformers instead of separated primary and secondary windings. The robust transistor configuration has facilitated the exploitation of the highest efficiency advantages of the pulsed autotransformer by removing the danger of turn-off voltage spike damage to the semiconductor device structures, which would be a hazard for unsnubbed conventional Darlington or gate turn-off thyristors. >

Development of a 10-kW solid state pulse power supply for copper vapor lasers

We have developed a magnetic-pulse-compression-type 10-kW-class solid state pulse power supply for copper vapor lasers. By triggering the gates of two gate turn-off thyristors (GTOs) connected in parallel, a 5-μs rise time primary pulse was generated. A three-stage magnetic pulse compression circuit compressed the primary pulse to 0.13 μs. The 13.7-kW GTO switching energy was achieved with a 4-kHz pulse repetition rate when a dummy load was connected instead of copper vapor laser (CVL). Total energy transfer efficiency of the power supply was 60%. This pulse power supply has been applied to a CVL with a plasma tube of 70-mm inner diameter and 1.5-m discharge length, and has operated successfully.

A near-zero current-switching series resonant inverter using GTOs

A novel implementation of fast gate-turn-off thyristors (GTOs) for a series resonant power converter operating above 10 kHz and an output power rating of 10 kW or greater is presented. A zero current switching gating strategy that eliminates the need for large negative gate drive circuits is presented. This permits the operation of the converter at a near-unity load power factor independent of the operating frequency. Consequently, for a given output power, the installed kVA capacity of the converter is minimized, and the system simplicity is maintained. A simplified analysis and component ratings for the GTO-based converter are presented. All the results are verified experimentally.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Snubber circuits and losses of voltage-source GTO inverters

The power dissipation of series and parallel snubbers in gate turn-off thyristor (GTO) inverters is investigated. New circuits using optimized snubbers are simulated and compared and solutions that allow the recovery of the energy stored in the snubbers are reported. In particular, an inverter circuit that uses a transformer for the recovery of the energy trapped in the snubbers is investigated, and solutions that avoid saturation of the transformer core are studied.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Evaluation of modern power semiconductor devices and future trends of converters

A review of the modern power semiconductor devices that appeared in the 1980s, i.e., the insulated gate bipolar transistor (IGBT), the static induction transistor (SIT), the static induction thyristor (SITH), and the MOS-controlled thyristor (MCT) is presented. The characteristics of these devices are discussed and compared from the viewpoint of power electronics applications. Although the IGBT is well known, the power electronics community is somewhat unfamiliar with the latter three devices. For completeness, a brief review of other power devices, such as the thyristor, the triac, the gate turnoff thyristor (GTO), the bipolar junction transistor (BJT), and the power MOSFET, is also incorporated. Finally, future converter trends are outlined. >

Influence of gate drive and anode circuit conditions on the turn-off performance of GTO thyristors

Measurements of anode current redistribution at turn-off are used to demonstrate the effect of different snubber circuit and gate drive conditions on the behaviour of a 56 mm, 1400 A, 2500 V GTO thyristor. The discussion offers a comprehensive explanation for the differences in device behaviour observed as both the turn-off gain and snubber capacitance are altered. Levels of redistribution are shown to be affected by the choice of snubber capacitance and level of snubber circuit stray inductance. Another important result shows that a low turn-off gain reduces the level of redistribution and thus allows the use of smaller snubber capacitors. Finally, it is concluded that even with continuing advances in devices manufacture, a close-coupled anode circuit design and high-performance gate drive are necessary for applications requiring a reduced snubber capacitance.

Performance analysis and circuit design of high-frequency resonant inverter using a single reverse-conducting device

This paper is concerned mainly with a performance analysis and a design method of a newly developed zero-current switching quasi-resonant high-frequency inverter (ZCS-QRI) using a single reverse-blocking power device (high-frequency GATT). As a matter of fact, GATT is replaced by the latest MOS-gate power semiconductor devices, MOSFET, IGBT, MCT and Bi-MOS · GTO thyristor. The frequency-modulated single-ended inverter circuit, which incorporates an auxiliary diode and large reactor cascade branch in parallel with a resonant capacitor connected into the transformer-link series-resonant tuned tank load circuit can stably and efficiently operate in the frequency range from 20 kHz up to 50 kHz or so. It is proved that the ZCS-QRI is more suitable for several kilowatt induction-heating and melting power supplies and high-intensity ultrasonic generator, and switched-mode dc-dc converters. This simple high-frequency ZCS-QRI for induction-heating load model is analyzed introducing normalized resonant and load circuit parameters and control variable on the basis of computer-aided simulation. The load and frequency regulation characteristics of ZCS-QRI and ZCS operating range are illustrated with a normalized expression in addition to voltage and current peak values and stresses of the power semiconductor device. The practical computer-aided design procedure using the inverter characteristics in steady-state expressed in the normalized technique is demonstrated and discussed including a design example. The simulation results of ZCS-QRI are illustrated and compared with the experimental results in trial-produced breadboard.

Optimal power control strategies for neutral point clamped (NPC) inverter topology

A programmed pulsewidth modulation (PWM) technique for selectively eliminating several lower-order harmonics at the output of a neutral point clamped (NPC) inverter topology is investigated. The switching function approach is utilized to derive relevant analytical expressions for input/output variables. A thorough evaluation of the NPC inverter topology based on the switching function approach is described. Optimal power control strategies for an NPC inverter employing programmed PWM patterns are proposed. For a constant-frequency variable-voltage NPC inverter power supply, the proposed strategy is to maintain a minimum specified total harmonic distortion employing a low-output impedance filter. In the case of an NPC inverter powering an AC motor drive, the proposed strategy is to maintain a minimum specified harmonic current factor. The proposed power control strategies are achieved without substantial increase in inverter switching frequency and are therefore suitable for high-power applications employing gate-turn-off-thyristor (GTO) type devices. >

A multiple PW GTO line-side converter for unity power factor and reduced harmonics

A multiple PWM GTO line-side converter with low switching frequency has been developed for industrial uses needing both higher capacity and higher performance. The multiple converter is composed of two GTO converter units connected in parallel through an interphase reactor. The switching frequency of the GTO thyristors in the multiple converter can be reduced to a quarter of that in the single converter. It is verified by simulations and experiments with a 2750 kVA GTO converter and inverter system with a 500 Hz switching frequency that the system has: (1) a unity power factor, (2) reduced harmonics, (3) bidirectional power flow, and (4) speed regulatory performance equal to that of an advanced cycloconverter drive system. Analogies between inverter control and converter control are also studied for the development of the converter control.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>