The manufacture of silicon power devices using welding techniques

Abstract

Epitaxial growth using chemical vapour deposition is the conventional manner for producing lightly doped silicon on more heavily doped substrates. With this technique it is difficult to achieve thick defect-free layers with high resistivity, and for interdigitated buried gate structure autodoping is a problem. A simpler and less expensive approach is the bonding together of two silicon wafers. The method employed is to polish the silicon surfaces to a roughness of less than 50 nm and to bring them together in a dust-free environment. In the present work, the wafers are cleaned, then washed and brought together in the wash bath to ensure minimum contamination. The bonded wafers are capable of withstanding all normal processing conditions, p-n diodes have been fabricated successfully with near ideal characteristics, and n-p-n bipolar transistors have been produced with the bonded interface in the p-base region. Whilst the density of recombination/generation centres at the bonded interface was around 5 × 10 11 cm −2 the average lifetime for minority carriers was 5 μs. By the addition of a p-type layer to the n-p-n transistors, gate turn-off thyristors have been produced successfully.