Gate Turn-off Research Articles

Physical insight into turn‐on transient of silicon carbide gate turn‐off thyristor

AbstractSilicon Carbide (SiC) Gate Turn‐off (GTO) thyristor is regarded as a promising option for pulsed power applications; however, the formation of high di/dt has been constrained by the slow current rise transient phase and the turn‐on current heterogeneity over the chip device. In this paper, a practical integrated multi‐cell simulation is performed to physically characterize the turn‐on transient of SiC GTO thyristor. Through examining electrical coupling between adjacent cells caused by both parasitics of electrode metallization and carrier travelling via SiC, the current distributions are observed, and the carrier transport dynamics are analyzed in detail. Furthermore, physical mechanisms dominating the current heterogeneity among multi‐cells are discovered in depth. It is revealed that the current heterogeneity during the turn‐on transient is primarily resulted from the Gate signal delay caused by the Gate Runner metallization, and the lateral interaction from adjacent semiconductor regions adds to this inhomogeneity; however, this situation can be improved once the electrical distance between each Anode contact and the Anode electrode gets lowered. Design method for turn‐on performance improvement is also proposed accordingly. Besides, based on the analysis conducted on the multi‐cell simulation results, the possible reason of the extremely slow current rise transient phase is speculated and experimentally verified. The improvement in the comprehension of SiC GTO's turn‐on transient, which cannot be obtained from the traditional investigation from the viewpoint of one elementary cell, will provide guiding principles helping in directing future efforts to advance the improvement of device design technology.

Simulation Study of 4H-SiC Low Turn-Off Loss and Snapback-Free Reverse-Conducting Gate Turn-Off Thyristor with N-Float Structure

In this study, a novel integrated 4H-SiC reverse-conducting gate turn-off thyristor (GTO) featuring an N-type floating (NF) structure is proposed. The proposed NF-structured 4H-SiC GTO outperforms conventional reverse-conducting GTOs in forward conduction, effectively eliminating the snapback phenomenon. This is achieved by increasing lateral resistance above the P-injector and modifying the electron current path during early turn-on. NF structures with a doping concentration of 2 × 1014 cm−3 and thicknesses exceeding 4 μm have been indicated to successfully eliminate the snapback phenomenon. Moreover, the anode-shorted structure enhances the GTO’s breakdown voltage and concurrently reduces turn-off losses by 85% at low current densities.

Technology and Applications of Wide Bandgap Semiconductor Materials: Current State and Future Trends

Silicon (Si)-based semiconductor devices have long dominated the power electronics industry and are used in almost every application involving power conversion. Examples of these include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), gate turn-off (GTO), thyristors, and bipolar junction transistor (BJTs). However, for many applications, power device requirements such as higher blocking voltage capability, higher switching frequencies, lower switching losses, higher temperature withstand, higher power density in power converters, and enhanced efficiency and reliability have reached a stage where the present Si-based power devices cannot cope with the growing demand and would usually require large, costly cooling systems and output filters to meet the requirements of the application. Wide bandgap (WBG) power semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and diamond (Dia) have recently emerged in the commercial market, with superior material properties that promise substantial performance improvements and are expected to gradually replace the traditional Si-based devices in various power electronics applications. WBG power devices can significantly improve the efficiency of power electronic converters by reducing losses and making power conversion devices smaller in size and weight. The aim of this paper is to highlight the technical and market potential of WBG semiconductors. A detailed short-term and long-term analysis is presented in terms of cost, energy impact, size, and efficiency improvement in various applications, including motor drives, automotive, data centers, aerospace, power systems, distributed energy systems, and consumer electronics. In addition, the paper highlights the benefits of WBG semiconductors in power conversion applications by considering the current and future market trends.

Enhancement of turn-off gate voltage waveform change by digital gate control for bond wire lift-off detection in IGBT module

The bond wire lift-off is the one of main failures for insulated gate bipolar transistors (IGBT) power modules. The wire lift-off increases parasitic inductance LeE in the module and the gate voltage Vge waveform is modulated by LeE·dIe/dt. Therefore, the Vge waveform has the potential for an indicator of condition monitoring. The Digital gate control (DGC) can control switching behavior precisely for low-loss and low-noise switching. It is also effective for sensitivity enhancement of Vge waveform changed by the wire lift-off. This paper reports how the DGC 2-step vector control (2-sVC) can improve the wire lift-off failure detection sensitivity by Vge waveform. The experiment results showed that the Vge spike was generated by LeE·dIe/dt at the turn-off switching and the spike generation timing depended on the wire number. The DGC obtained the larger timing-shift Δtwire and the amplitude ΔVge-surge than those at the conventional gate control. In addition, the best vector condition improved the trade-off between turn-off loss and collector voltage overshoot compared with the conventional gate control. From these results, the DGC is effective to enhance the sensitivity of bond wire lift-off detection by Vge waveform maintaining the best switching performance.

On the Frequency Dependence of the Gate Switching Instability in Silicon Carbide MOSFETs

Silicon carbide power metal-oxide semiconductor field-effect transistors (MOSFETs) are suitable for more compact and energy efficient electric power conversion, pushing forward numerous key technologies in emission-free mobility and green power generation. These applications require fast gate switching up to hundreds of kilohertz. Typically, to assure a clear turn-off state of the electron channel, a negative turn-off gate bias is used in conjunction with a positive turn-on gate bias. Recently, several reports have revealed a new and so far unknown degradation mechanism that emerges during such operation conditions in apparently all commercial silicon carbide MOSFETs. As this mechanism arises upon gate switching, the terms gate switching instability (GSI) and gate switching stress (GSS) for the mechanism and the associated stress, respectively, have been introduced.Here, we show that this degradation mechanism does not depend on the used frequency up to at least 2 MHz, but that it is actually related to the cumulative number of switching cycles. For this purpose, we performed measurements at various frequencies comprising ultra-fast in-situ measurements of the threshold voltage and pre- and post-stress characterization by impedance analysis. The results are important both for understanding the underlying physics and for developing a correct methodology for industrial device qualification.

Impact of Turn-Off Gate Voltage and Temperature on Threshold Voltage Instability in Pulsed Gate Voltage Stresses of SiC MOSFETs

Bias temperature instability (BTI) in SiC MOSFETs has come under significant academic and industrial research. Threshold voltage (VTH) shift due to gate voltage stress has been demonstrated in several studies investigating gate oxide reliability in SiC MOSFETs. Results have shown positive.VTH shift occurs due to electron trapping (PBTI), and negative VTH shift occurs due to hole trapping (NBTI). In this paper, VTH shift is studied for unipolar and bipolar gate pulses with frequencies ranging from 1Hz to 100 kHz. The turn-OFF voltage for the unipolar VGS pulse is 0 V. In the case of the bipolar VGS pulses, two turn-OFF voltages are investigated, namely VGS-OFF = -3V and VGS-OFF= -5V. VTH shift is measured after 1000 seconds with recovery times in the range of 20 milliseconds, and preconditioning is performed before VTH measurement. These measurements have been performed at 25°C and 150°C on a commercially available SiC Planar MOSFET and a SiC Trench MOSFET. The results show that -3 V is enough for de-trapping sufficient electrons while -5V results in increased NBTI, which is accelerated by higher temperatures.

Investigation of Off-State Stress Induced Degradation of SiC MOSFETs Under Short-Circuit Condition

Investigation of SiC MOSFETs short-circuit (SC) degradation mechanism is critical to improve the overall reliability of power converters. At present, research on the SiC MOSFETs degradation mechanism mainly focuses on the on-state phase of the SC period. While, ruggedness of SiC MOSFETs in the off-state phase of short-circuit tests (SCTs) were neglected. In this paper, SiC MOSFETs degradation mechanism in the off-state phase of SCTs are investigated comprehensively. Specifically, distribution and magnitude of electrothermal stress of devices under test (DUTs) in the off-state phase of SCTs are analyzed by TCAD simulation. Which reveals two important phenomena: i) the device will suffer from long-term high temperature and high electric field stress in the off-state phase when negative turn-off gate voltage (Vgs-off) is applied; ii) high hole current in the channel region will last for several microseconds after the device is turned off. The observed SiC MOSFETs degradation in the off-state phase of SCTs is then proved by experiments, through which, the excessively low Vgs-off can reduce the SC capability of SiC MOSFETs is concluded. Moreover, the degradation results of static parameters of SiC MOSFETs are presented and the degradation mechanism is analyzed in detail.

Modeling and Analysis of SiC GTO Thyristor’s Dynamic Turn-On Transient

The fast turn-on speed of silicon carbide (SiC) gate-turn-off (GTO) thyristor is preferred for pulse power applications. However, the turn-on delay phenomenon hinders its improvement. In this article, the dynamic turn-on transient process of SiC GTO thyristor is investigated and analyzed extensively by means of both numerical simulation and physical modeling. The physical mechanism behind its turn-on transient process is discussed in detail. A physical model based on the charge-control theory is proposed to identify the dominant factors influencing the dynamic turn-on transient. Then the theoretical analysis is quantitatively made on the parameter design of GTO’s unit cell, and methods to increase the turn-on switch speed are extensively discussed. This study provides not only in-depth physical insights into the device’s turn-on characteristics, but also designs guidelines for the advancement of SiC GTO thyristor.

Comparative Model of Single-phase AC Cycloconverter for 1000Wp Photovoltaic Grid-connected 220VAC-50Hz

Currently, the Electrical Engineering Laboratory (EEL) of Universitas Jenderal Achmad Yani has a 1 kWp photovoltaic (PV) system. However, in order to fulfill the overall load, the hybrid link to the grid must be improved. The PV system and the grid must be synchronized in terms of voltage, frequency, and phase. This article presents comparative simulations of AC-AC converter models of power electronics component variants using MATLAB 2019a. Among other stages is to model the DC-DC Converter in order to enhance the output voltage of the solar panel by identifying the circuit characteristics. The second stage involves simulating the MOSFET-based DC-AC Converter circuit, which is used to convert DC to AC. The use of switching Thyristor, Gate Turn-Off Thyristor (GTO), and Insulated Gate Bipolar Transistor (IGBT) in an AC-AC phase converter to connect to the grid is examined in this range. Non-linear and linear loads are used to represent the load on the AC Cycloconverter range. Based on the results of the modeling and analysis of the PV 1 kWp system, the AC Cycloconverter in the first stage may provide a frequency of 50 Hz with a voltage drop of 235.4 V for the line and 231.9 V for the non-linear, which meets the AC Cycloconverter criterion.

Behavior, Switching Losses, and Efficiency Enhancement Potentials of 1200 V SiC Power Devices for Hard-Switched Power Converters

Semiconductor power devices are the major constituents of any power conversion system. These systems are faced by many circumscriptions due to the operating constraints of silicon (Si) based semiconductors under certain conditions. The emergence and persistence evolution of wide bandgap technology pledge to transcend the restrictions imposed by Si based semiconductors. This paper presents a thorough experimental study and assessment of the performance of three power devices: 1200 V SiC cascode, 1200 V SiC MOSFET, and 1200 V Si IGBT under the same hardware setup. The study aims to capture the major attributes for each power device toward determining their realistic potential applications. The switching performance of each power device is studied and reported. As the gate resistance is a crucial factor in a power device characterization, an extensive analysis of hard-switching losses under different separated turn-on and turn-off gate resistances is also performed and discussed. To appraise the fast switching capability, the switching dv/dts and di/dts are measured and analyzed for each power device. Furthermore, insights are provided about the dependency of switching energy losses on the power device current and blocking voltage. This paper also focuses on evaluating the operations and the performances of these power devices in a hard-switched dc-dc converter topology. While using of 1200 V SiC Schottky diode in the converter design with each power device, the high switching frequency operations and efficiency of the converter are reported and thoroughly explored. The SiC cascode exhibited superior performance when compared to the other two power devices. The results and analyses represent guidelines and prospects for designing advanced power conversion systems.

Evaluation of Ultrahigh-Voltage 4H-SiC Gate Turn-OFF Thyristors and Insulated-Gate Bipolar Transistors for High-Power Applications

Technology-based computer-aided design models have been used to predict the static and dynamic performance of ultrahigh-voltage (UHV) 4H-silicon carbide (SiC) P-i-N diodes, insulated-gate bipolar transistors (IGBTs), and gate turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> (GTO) thyristors designed for 20–50 kV blocking voltage capability. The simulated forward voltage drops of 20–50 kV device designs range between 3.1 and 5.6 V for P-i-N diodes, 4.2–10.0 V for IGBTs, and 3.4–7.8 V for GTO thyristors at 20 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for room temperature operation. Moreover, with a low switching frequency application (i.e., 150 Hz) in mind, the switching energy losses using a 30 kV SiC GTO thyristor design are approximately E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> _ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GTO</sub> = 268/640 mJ, E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> _ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FWD</sub> = 388/6 mJ diode recovery losses, and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> _ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SNUB</sub> = 954/22 mJ snubber component losses. The corresponding values for an SiC IGBT design are <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> _ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IGBT</sub> = 983/748 mJ, both operated at 448 K, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">τ_A</i> = 20 μs, and with 30 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The simulation output is used in a benchmark evaluation for a 1 GW, 640 kV application case, employing modular multilevel high-power converter legs comprising series-connected UHV SiC devices and state-of-the-art 4.5 kV Si bi-mode insulated-gate transistors. It is concluded that the high-voltage SiC power electronic building blocks present promising alternatives to existing high-voltage Si device counterparts in terms of system compactness and efficiency.

Optimization techniques for p-GTO thyristor design

A new type of semiconductor power device was devised in the early ’90s as an alternative to the classic Gate Turn-Off (GTO) thyristor. Because the low-doped n-base was replaced by a low-doped p-base, it was called the p-GTO. Its main advantage is a higher possible control voltage when the device is switched off, leading to the possibility of a higher blocking anode current (IATO) and a lower turn-off time. The studies and techniques employed with the help of SILVACO-TCAD simulation software Athena and Atlas show that the p-GTO has higher breakdown voltages compared with its classic counterpart and similar on-state voltage (VT) and switching characteristics when replacing the GTO in the same circuit. Specific circuit improvements, like an affordable higher turn-off gate voltage, will drive the p-GTO into even faster switching operation.

Enhancing gate turn-off thyristor blocking characteristics by low temperature defect passivation technology

In the past, gate turn-off (GTO) thyristors were commonly used to either increase the length of the drift region or reduce the doping concentration to increase high-voltage and high-power applications. However, this results in an on-resistance (R on) increase. In this study, we applied a supercritical fluid (SCF) treatment to devices which has the advantage of high permeability and low-temperature processing to passivate SiC-GTO bulk defects. After the proposed defect passivation, the breakdown voltage has been improved by 8% without increasing on-state resistance. In addition, the leakage current has also been suppressed more than 30% in average. This study also uses electrical analysis to understand the characteristics of the devices after SCF treatment, and then discusses the passivation mechanism of materials of the devices from this treatment.

Atomistic Mechanism of 4 H - SiC/SiO2 Interface Carrier-Trapping Effects on Breakdown-Voltage Degradation in Power Devices

The $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface in the termination area is a crucial component in limiting high-temperature reverse-bias (HTRB) reliability for $\mathrm{Si}\mathrm{C}$-based high-voltage devices. However, the atomic structure and carrier-trapping behavior of the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defects therein and the underlying physical mechanisms of breakdown-voltage (${V}_{\mathrm{BD}}$) variation are still largely unclear. Here, the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defects of 4H-$\mathrm{Si}\mathrm{C}$ gate turn-off (GTO) thyristors before and after HTRB stress are investigated by transient capacitance measurements and density-functional-theory (DFT) calculations. It is found that the bias stress at 4.4 kV enlarges the interface state density at ${E}_{C}\ensuremath{-}0.60$ eV to ${E}_{C}\ensuremath{-}1.33$ eV by electron capturing. As a result, the negative interface charge is generated. As high-resolution transmission electron microscopy reveals the presence of excess carbon near the $\mathrm{Si}\mathrm{C}$ surface, DFT calculations are focused on carbon-related interface defects to clarify the atomic and electronic structures of the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface trap and assign them to negatively charged excess split-interstitial carbon at the interface. Furthermore, technical computer-aided-design simulation further proves that the negatively charged $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defect is the main cause for the observed ${V}_{\mathrm{BD}}$ degradation after the HTRB test, which leads to a strong electric field crowding effect. These results not only provide deep physical insights underlying ${V}_{\mathrm{BD}}$ degradation in HTRB-stressed high-voltage devices, but are also of significant importance in the optimizations of device structure and oxidation technology for $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interfaces in high-voltage $\mathrm{Si}\mathrm{C}$ devices.

A High-Resolution In Situ Condition Monitoring Circuit for SiC Gate Turn-Off Thyristor in Grid Applications

Silicon carbide (SiC) gate turn-off (GTO) thyristor is attractive for grid applications due to the excellent performances of high blocking voltage and low ON-resistance. However, the short-circuit reliability issue has become one of the limiting factors. An in situ condition monitoring method for the reliability of SiC GTO is presented in this work. It uses the forward I- V characteristics of anode-gate p-n junction as the reliability degradation precursor of SiC GTO. The monitoring circuit shows a current resolution of 64 μA with the current range of -31~1027 mA. It provides full electrical isolation with 2-kV isolation voltage. Finally, a set of short-circuit power cycling tests are conducted with the monitoring circuit, and the results show that the method proposed in this article can effectively detect the change of I- V characteristics of SiC GTO to predict the degradation of device physical health.

Investigation of Dynamic Temperature-Sensitive Electrical Parameters for Medium-Voltage SiC and Si Devices

This article presents six groups of dynamic temperature-sensitive electrical parameters (TSEPs) for the medium-voltage silicon carbide (SiC) and silicon (Si) devices. The physical mechanisms of the temperature dependence of these parameters are analyzed with the difference between SiC and Si devices highlighted. A test platform is developed that enables implementation of the temperature relevant dynamic characterization. The investigated TSEPs are summarized in terms of their relationship with junction temperature, load current, dc voltage, and external gate resistance. The impact of the parasitic parameters on the evaluation results is analyzed. The comparison between 3.3-kV 5-A SiC MOSFETs and 3-kV 12-A Si insulated-gate bipolar transistors (IGBTs) is conducted. The results verify that for the medium-voltage SiC MOSFETs, the turn-off drain–source voltage switching rate, the turn-off gate current peak value, and the turn-on gate current plateau achieve better thermal sensitivity, in comparison with the Si IGBTs. The turn-off and turn-on delay time exhibit better thermal linearity compared with other investigated TSEPs.

Surface Recombination and Excess Current of Anode-Gate Mesa Sidewall in 4H-SiC Gate Turn-Off Thyristor

The forward and reverse I-V characteristics of Anode-Gate diodes passivated with pyrogenic and dry oxide in4H-SiC gate turn-off thyristor (GTO) were investigated by device size dependent measurement. The bulk and surface current component were manifested and separated, where the surface recombination velocity was accurately evaluated as 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> -10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cm/s. Pyrogenic oxide was found more effective than dry oxide to suppress surface traps induced excess carrier recombination and carrier generation at etched p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> n mesa sidewall. Moreover, temperature dependent measurement revealed that excess current of Anode-Gate diodes is primarily attributed to carrier recombination and generation from surface traps. Surface traps dominates the reverse leakage below 125 °C, while electrically active bulk defects contributes to the reverse leakage simultaneously at elevated temperature. Finally, the influence of passivation on the 4H-SiC GTOs forward characteristics was demonstrated. Higher gate trigger current needed to switch from blocking to conduction state for the 4H-SiC GTOs with dry oxide passivated Anode-Gate mesa sidewall.

New Hybrid Superconducting Fault Current Limiter For Primary Distribution Systems (Dept.E)

In this paper, a new hybrid fault current limiter is proposed for primary distribution systems. It incorporates a high temperature superconducting element in parallel with other two branches. The first is an inductive impedance to share the fault current with. The second branch is a gate-turn off thyristor switch controlled to operate the device in either of two modes: the main mode and the stand-by mode. For the main mode, it controls the temperature of the superconducting element and protects it against damaging excessive heating. Instead, in the stand-by mode, it keeps the device applicable without that superconducting element. The design, control and operation of the device is addressed. Its performance in 11 kV distribution systems with DG is investigated. The effect of fault location and fault incidence angle on the device behavior are explored.

Investigating the Failure Mechanism of Short-Circuit Tests in 1.2-kV SiC JBS-Integrated MOSFETs

In this article, the failure mechanism of a 1.2-kV monolithic junction barrier-controlled Schottky diode integrated silicon carbide metal–oxide–semiconductor field-effect transistor (JMOS) under short-circuit (SC) tests has been investigated by an experimental validation and simulation analysis. As a new type of device, JMOS has superior performance and chip area efficiency. However, the SC ruggedness of the JMOS needs further investigation. When comparing vertical double-diffused metal–oxide–semiconductor field-effect transistor (VDMOS) and JMOS devices in the SC test study, the leakage current of the JMOS is much higher than that of a common VDMOS. During the SC test, the JMOS drain current cannot be successfully suppressed after gate turn-off, and the thermionic emission current due to heat generation in the Schottky barrier diode (SBD) region continues flowing into the n-drift region. The SBD thermionic emission current is rapidly increased by the increasing lattice temperature, which can reach over 1600 K. Eventually, the JMOS undergoes thermal runaway due to positive electrothermal feedback. A mechanistic study was set up to analyze the relationship between the SC limit and the leakage current in the SBD region of the heated materials. Finally, the key to improve the SC ruggedness of the JMOS is decreasing the leakage current in the SBD region.

Investigation on 4H-SiC gate turn-off thyristor with direct carrier extraction access to drift region for power conversion applications

4H-SiC gate turn-off (GTO) thyristor offers extraordinary advantages over its counterparts in handling ultra-high voltage electric power conversion applications because of its relatively low forward voltage drop at high conduction current density. Besides, though the SiC thyristors never suffer from long carrier liftime induced large switching loss like Si thyristors, the peak temperature rise rather than dynamic avalanche breakdown is blamed for the safe operation area (SOA) failure, making further reduction of power loss in SiC GTOs even more important. In this paper, a 20 kV SiC GTO with direct carrier extraction access to its drift region (DA-GTO) is investigated to explore the benefit this structure could bring for SiC thyristors, namely achieving smaller switching loss and/or potential larger SOA with slight sacrifice in forward voltage drop at high current. The structure is formed by interleaved P+ ion implantation into part of the thin N-injector layer based on conventional 20 kV SiC GTO. The SiC DA-GTO operates in BJT mode at low current, and in GTO mode with low forward voltage drop at high current. During turn-off process, it offers a direct current path to quickly sweep out the excess carriers in the P-drift region, thus speeds up the turn-off process and decreases the turn-off loss. Simulation results show that its turn-off loss reduces by 37.4%, contributing to 12.6% reduction in total power loss, compared with SiC GTO. Therefore, SiC DA-GTO is a very promising choice for next-generation power conversion systems.