Gate Threshold Voltage Research Articles

Measurement and analysis of SiC-MOSFET threshold voltage shift

Silicon carbide power MOSFETs are used in numerous studies to improve the efficiency or the performance of power electronic converters. However, the gate-oxide technology weakness is a main reliability issue of silicon carbide MOSFET transistors. The threshold voltage shift is a critical phenomenon that addresses the reliability of industrial power applications. It is important to have a better understanding of the phenomena implied in the gate threshold voltage shift. In this context, a static ageing test based on JEDEC standard is proposed and the resulting gate oxide stress is studied and discussed in this paper. Complementary testing was performed with dynamic reliability and gate oxide characterizations, such as the charge pumping technique. The results obtained are used to add insight to the current discussion of SiC MOSFET robustness. Additionally test benches and measurement protocols established on 1.7 kV 45 mΩ are detailed, which will be useful for the next generation of SiC MOSFET.

Phase Modulators Based on High Mobility Ambipolar ReSe2 Field-Effect Transistors

We fabricated ambipolar field-effect transistors (FETs) from multi-layered triclinic ReSe2, mechanically exfoliated onto a SiO2 layer grown on p-doped Si. In contrast to previous reports on thin layers (~2 to 3 layers), we extract field-effect carrier mobilities in excess of 102 cm2/Vs at room temperature in crystals with nearly ~10 atomic layers. These thicker FETs also show nearly zero threshold gate voltage for conduction and high ON to OFF current ratios when compared to the FETs built from thinner layers. We also demonstrate that it is possible to utilize this ambipolarity to fabricate logical elements or digital synthesizers. For instance, we demonstrate that one can produce simple, gate-voltage tunable phase modulators with the ability to shift the phase of the input signal by either 90° or nearly 180°. Given that it is possible to engineer these same elements with improved architectures, for example on h-BN in order to decrease the threshold gate voltage and increase the carrier mobilities, it is possible to improve their characteristics in order to engineer ultra-thin layered logic elements based on ReSe2.

Efficient ab initio analysis of quantum confinement and band structure effects in ultra-scaled Si1−xGex gate-all-around and fin field-effect transistors for sub-10 nm technology nodes

This paper analyzes the sub-10 nm ultra-scaled Si1−xGex fin field-effect transistor (FinFET) and gate-all-around transistor (GAAFET), based on an improved method by combining Slater partial occupation and ab initio density functional theory (DFT). Compared to the existing generalized gradient approximation (GGA) DFT, which is computationally efficient but inaccurate, and the established hybrid functional DFT, which is accurate but computationally demanding, the proposed method achieves both hybrid functional-like high accuracy and GGA-like high computational efficiency concurrently. By using this improved methodology, batch simulations are performed to investigate the size- and composition-dependent quantum confinement and band structure effects in the Si1−xGex FinFET and GAAFET. It is shown that the quantum confinement in ultra-scaled FinFET and GAAFET significantly increases the bandgap of Si1−xGex channel in the sub-10 nm scale. It is quantitatively demonstrated that, due to its two-dimensional quantum confinement, the ultra-scaled GAAFET has larger confinement-induced bandgap increase, lower direct source-drain quantum tunneling, lower off-state transmission and low-bias conductance, and smaller drain-induced barrier lowering, compared to the FinFET which is confined only in one-dimension. These differences jointly indicate that the ultra-scaled GAAFET could offer better device performance than the ultra-scaled FinFET. It is quantitatively shown that, by reducing the Ge composition of the Si1−xGex channel in ultra-scaled FinFET and GAAFET, the bandgap and the threshold gate voltage can be significantly increased; and the transmission coefficients, the low-bias conductance, and the source-drain current can be significantly reduced. These trends can be utilized to optimize device performance by tuning Ge composition in different technology nodes.

4600 V Sic Dmosfets with R<sub>DS,On</sub> = 17 mΩ-cm<sup>2</sup>

Large-area, 7.84 mm2 SiC DMOSFETs feature breakdown voltages of 4600 V, specific on-resistance of 17 mΩ-cm2 and gate threshold voltage of 2.4 V. The low on-resistance was enabled by an optimized MOS process that resulted in channel mobility as high as 27 cm2/Vs, and oxide breakdown fields in the 10-11 MV/cm range. The key device design and layout parameters were varied to examine the performance versus reliability trade-offs.

Role of Biasing and Device Size on Phonon Scattering in Graphene Nanoribbon Transistors

We study the noncoherent transport due to electron–phonon (e-ph) interaction in graphene nanoribbon (GNR) field-effect transistors (GNRFETs) using nonequilibrium Green’s function method in mode space. Phonon dispersion calculations in conjunction with the e-ph interaction computations show that in an armchair GNR, only a small number of phonon modes are coupled to the carriers. Our simulation shows that under a threshold gate voltage, the drain–source current is diminished by the low-energy phonons such as acoustic phonon modes and radial-breathing-like phonon modes, while at great biases of the gate, the current drop is essentially due to high-energy optical phonon modes. The effect of drain voltage on scattering process is discussed, which shows that at higher drain voltages, the ballisticity decreases. We also explore the phonon scattering dependence on the dimensions of GNRFET channel. In larger width ribbon, the impact of phonon scattering decreases. The channel with a length of 30 nm is ballistic up to 90%, and only when its length is increased to approximately 180 nm, transport becomes semiballistic, which infers to an effective mean free path of ~200 nm.

Model for Charge Accumulation in n- and p-MOS Transistors during Tunneling Electron Injection from a Gate

A quantitative model for charge accumulation in an undergate dielectric during tunneling electron injection from a gate according to the Fowler–Nordheim mechanism is developed. The model takes into account electron and hole capture at hydrogen-free and hydrogen-related traps as well as the generation of surface states during the interaction of holes with hydrogen-related centers. The experimental dependences of the threshold voltage shift and gate voltage shift of n- and p-channel MOS (metal–oxide–semiconductor) transistors on the injected charge in the constant current mode are analyzed based on the model.

Metal Semiconductor Field Effect Transistors with Conducting NbS2/n-MoS2 Van Der Waals Schottky Junction and Graphene Contact

We have fabricated van der Waals (vdW) Schottky junction between high work function conducting NbS2 transition metal dichalcogenide (TMD) and semiconducting n-MoS2 TMD for metal semiconductor field effect transistors (MESFETs). The Schottky barrier between NbS2 and MoS2 appeared as large as ~0.5 eV due to their work function difference, as measured by scanning Kelvin probe. Schottky effect MESFET operates with a low threshold gate voltage of -0.5 ~ -1 V exhibiting easy saturation. Since this FET contains low density traps at the vdW interface, little gate hysteresis and ideal subthreshold swing of 60~80 mV/dec are expected. In addition, source/drain (S/D) contact for n-channel MoS2 could significantly affect device mobility. In the case of the graphene S/D contact, the device shows the highest mobility of more than 800 cm2/V s, although the device shows the lowest mobility of ~15 cm2/V s in the case of Au/MoS2 contact without an annealing process. TMD-based MESFET with NbS2/n-MoS2 junction is considered novel and promising in future 2D device electronics.

Characterization of SiO2/SiC interface states and channel mobility from MOSFET characteristics including variable-range hopping at cryogenic temperature

The characteristics of SiC MOSFETs (drain current vs. gate voltage) were measured at 0.14−350 K and analyzed considering variable-range hopping conduction through interface states. The total interface state density was determined to be 5.4×1012 cm−2 from the additional shift in the threshold gate voltage with a temperature change. The wave-function size of interface states was determined from the temperature dependence of the measured hopping current and was comparable to the theoretical value. The channel mobility was approximately 100 cm2V−1s−1 and was almost independent of temperature.

GaN‐based complementary metal–oxide–semiconductor inverter with normally off Pch and Nch MOSFETs fabricated using polarisation‐induced holes and electron channels

Gallium nitride (GaN)-based P-channel (Pch) and N-channel (Nch) metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off operations were realised. Both Pch and Nch MOSFETs were monolithically fabricated in a polarisation-junction platform wafer. The platform wafer was constructed with a GaN/aluminium GaN/GaN double heterostructure, which has both two-dimensional hole gas (2DHG) and 2D electron gas (2DEG). The drain currents of Pch and Nch MOSFETs flow through 2DHG and 2DEG, respectively. The threshold gate voltages of the fabricated Pch and Nch MOSFETs were -2.7 and 6.7 V, respectively. It was shown that the threshold voltage and the on-state resistance of the Pch MOSFET can be controlled by adjusting the 2DEG potential. Furthermore, using Pch and Nch MOSFETs, complementary MOS inverter operation was demonstrated.

Low power FGMOS-based four-quadrant current multiplier circuits

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the − 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered.

Vertical and In-Plane Current Devices Using NbS2/n-MoS2 van der Waals Schottky Junction and Graphene Contact.

A van der Waals (vdW) Schottky junction between two-dimensional (2D) transition metal dichalcogenides (TMDs) is introduced here for both vertical and in-plane current devices: Schottky diodes and metal semiconductor field-effect transistors (MESFETs). The Schottky barrier between conducting NbS2 and semiconducting n-MoS2 appeared to be as large as ∼0.5 eV due to their work-function difference. While the Schottky diode shows an ideality factor of 1.8-4.0 with an on-to-off current ratio of 103-105, Schottky-effect MESFET displays little gate hysteresis and an ideal subthreshold swing of 60-80 mV/dec due to low-density traps at the vdW interface. All MESFETs operate with a low threshold gate voltage of -0.5 ∼ -1 V, exhibiting easy saturation. It was also found that the device mobility is significantly dependent on the condition of source/drain (S/D) contact for n-channel MoS2. The highest room temperature mobility in MESFET reaches to approximately more than 800 cm2/V s with graphene S/D contact. The NbS2/n-MoS2 MESFET with graphene was successfully integrated into an organic piezoelectric touch sensor circuit with green OLED indicator, exploiting its predictable small threshold voltage, while NbS2/n-MoS2 Schottky diodes with graphene were applied to extract doping concentrations in MoS2 channel.

Modeling and Characterization of Inconsistent Behavior of Gate Leakage Current with Threshold Voltage for Nano MOSFETs

A strange relationship of gate leakage current and threshold voltage variation for nano MOSFETs is analyzed using factual strategy and subsequently a physical model is proffered. The gate leakage current increments with the threshold voltage before it diminishes at higher threshold voltage in nanoscale devices. This inconsistent behavior of gate leakage current with threshold voltage variations is precisely clarified in the manuscript through the concept of accord between two contrary operations: threshold voltage roll-off impact and gate leakage current reliance on surface potential. The tunneling gate leakage current density diminishes with threshold voltage over surface potential. However, the threshold voltage roll-off impact causes higher threshold voltage for larger channel length devices. The net gate leakage current is adjusted by these two contrary functions of threshold voltage. In addition, the rate of accretion of the gate leakage current with threshold voltage variation is also analyzed. The impact of the increase in the power supply voltage on the rate of accretion of the gate leakage current vs. threshold voltage curve is also explored. Thorough methodical TCAD simulations are accomplished to validate the proffered models. Both the experimental outcomes, TCAD simulations and physics based models are implemented to uncover and clarify the threshold voltage gate leakage relationship, particularly for nano MOSFETs. The proposed notion is not currently captured in conventional gate leakage nano device models, hence the proffered physical models may be utilized in progression of reliable and trustworthy TCAD simulation tools for nano devices.

Модель накопления зарядов в n- и p-МОП-транзисторах при туннельной инжекции электронов из затвора

AbstractA quantitative model for charge accumulation in an undergate dielectric during tunneling electron injection from a gate according to the Fowler–Nordheim mechanism is developed. The model takes into account electron and hole capture at hydrogen-free and hydrogen-related traps as well as the generation of surface states during the interaction of holes with hydrogen-related centers. The experimental dependences of the threshold voltage shift and gate voltage shift of n - and p -channel MOS (metal–oxide–semiconductor) transistors on the injected charge in the constant current mode are analyzed based on the model.

Design Considerations for Gan-Based Microinverter for Energy Storage Integration Into Ac Grid

Abstract A full bridge converter with electrolytic capacitor on the dc bus is a widely used approach for a single phase interface for renewable energy source generation or energy storage integration in the utility grid. New wide bandgap devices enable higher switching frequency, higher efficiency and higher power density. In the paper, the authors introduce the challenges associated with an increase in switching frequency of a single phase inverter and implementation of wide bandgap GaN-based transistors instead of traditional Si-based transistors. The low gate threshold voltage of GaN transistor and unique reverse conduction behaviour require different driving circuit. The design of the driver circuit and other practical issues are analysed in the paper. The paper also presents some practical results. The research results can be useful to avoid mistakes by designing GaN-based power converters as these devices become increasingly interesting for commercial applications.

Experimental and Numerical Investigation of Contact Doping Effects in Dinaphthothienothiphene Thin‐Film Transistors

SUMMARYContact doping effects in p‐channel dinaphthothienothiphene (DNTT) thin‐film transistors with a bottom‐gate, top‐contact configuration were investigated with both experimental and numerical approach. Characteristic variation in transistor parameters such as the gate threshold voltage and the field‐effect mobility for devices with various channel lengths was suppressed by the contact doping with tetrafluorotetracyanoquinodimethane (F4TCNQ) as an acceptor dopant. The gate‐voltage dependence of contact resistance and channel resistance was also evaluated separately to examine the contact doping effect in detail. In addition, device simulation considering a Schottky barrier at a metal/semiconductor interface successfully reproduced the experimental current–voltage characteristics by using a hole concentration of the active DNTT layer in the order of 1017 cm−3, which was estimated by capacitance–voltage measurement for a metal/insulator/semiconductor capacitor structure. This study suggests the importance of establishing both the carrier doping and carrier concentration measurements toward realizing practical applications of organic transistors.

Radiation induced transconductance overshoot in the 130 nm partially-depleted SOI MOSFETs

This paper presents the total ionizing dose (TID) radiation performances of core and input/output (I/O) MOSFETs from 130nm partially-depleted silicon-on-insulator (PDSOI). Both the core NMOS and PMOS are totally hardened to 1.5Mrad(Si), while the I/O devices are still sensitive to TID effect. The worst performance degradation is observed in I/O PMOS which is manifested as significant front gate threshold voltage shift and transconductance decrease. Contrary to PMOS, front gate transconductance overshoot is observed in short channel I/O NMOS after irradiation. A radiation induced localized damage model is proposed to explain this anomalous phenomenon. According to this model, the increments of transconductance depend on the extension distance and trapped charge density of the localized damage region in gate oxide. More trapped charge lead to more transconductance increase. These conclusions are also verified by the TCAD simulations. Furthermore, the model presents a way to extract the trapped charge density in the localized damage region.

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

Photodoping-Driven Crossover in the Low-Frequency Noise of MoS2 Transistors

Transition metal dichalcogenide field-effect transistors (FETs) have been actively explored for low-power electronics, light detection, and sensing. Albeit promising, their performance is strongly limited by low-frequency noise (LFN). Here, we report on the study of LFN in MoS$_2$ FETs on SiO$_2$ substrates in ambient conditions using photodoping. Using this external excitation source allows us to access different non-equilibrium steady states and cross over different noise regimes. We observe a dependence of the noise power spectrum with the transient decay time window, approaching $1/f$-type when the system is closer to equilibrium, and identify a dependence of the LFN with channel thickness. Monolayer/bilayer devices exhibit random telegraph noise for insulating regimes and $1/f$-type Hooge mobility fluctuations (HMF) for conductive regimes. Thicker devices exhibit mainly $1/f$-type carrier number fluctuations (CNF). In the latter, we observe a photodoping-induced change from a near parabolic to a near linear dependence of the inverse $1/f$ noise amplitude above the threshold gate voltage. This change indicates a crossover in the LFN mechanism from CNF to HMF. We demonstrate that the study of conductance and noise under photodoping is an effective tool to identify dominating carrier noise mechanisms in few-atomic-layer FETs for a wide range of doping regimes.

Normally-Off C–H Diamond MOSFETs With Partial C–O Channel Achieving 2-kV Breakdown Voltage

Diamond has unique physical properties, which show great promise for applications in the next generation power devices. Hydrogen-terminated (C–H) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) often have normally-on operation in devices, because the C–H channel features a p-type inversion layer; however, normally-off devices are preferable in power MOSFETs from the viewpoint of fail safety. We fabricated hydrogen-terminated (C–H) diamond MOSFETs using a partially oxidized (partial C–O) channel. The fabricated MOSFETs showed a high breakdown voltage of over 2 kV at room temperature and normally-off characteristics with a gate threshold voltage $\text{V}_{\mathrm{th}}$ of −2.5–−4 V.

Drain Current Model for Double Gate (DG) p-n-i-n TFET: Accumulation to Inversion Region of Operation

In this paper, drain current model has been formulated for Double Gate (DG) p-n-i-n Tunnel FET (TFET) using Lambert-W function. The model includes the impact of mobile charges, gate dielectric thickness (tox) and channel thickness (tsi) on quasi fermi level, gate threshold voltage (VTG), onset voltage (VGonset) and Tunneling Barrier Width (TBW) over the entire operating range i.e. accumulation to inversion state. Important electrostatic and electrical parameters such as the effective potential (φeffective) at the center of the channel, 2-D channel potential, electric field, energy band profile and Tunneling Barrier Width (TBW) dependent drain current have been modeled. Moreover, gate and drain bias controllability in different operating regimes has also been investigated by varying oxide thickness (tox), channel thickness (tsi), intrinsic channel length (Lint) and at different temperatures. Important FOMs required for analog circuit performance such as transconductance (gm), drain conductance (gd), output resistance (Rout), early voltage (VEA) have also been evaluated and verified using ATLAS device simulation software.