Gate Threshold Voltage Research Articles

Hall and field-effect mobilities in few layered p-WSe₂ field-effect transistors.

Here, we present a temperature (T) dependent comparison between field-effect and Hall mobilities in field-effect transistors based on few-layered WSe2 exfoliated onto SiO2. Without dielectric engineering and beyond a T-dependent threshold gate-voltage, we observe maximum hole mobilities approaching 350 cm2/Vs at T = 300 K. The hole Hall mobility reaches a maximum value of 650 cm2/Vs as T is lowered below ~150 K, indicating that insofar WSe2-based field-effect transistors (FETs) display the largest Hall mobilities among the transition metal dichalcogenides. The gate capacitance, as extracted from the Hall-effect, reveals the presence of spurious charges in the channel, while the two-terminal sheet resistivity displays two-dimensional variable-range hopping behavior, indicating carrier localization induced by disorder at the interface between WSe2 and SiO2. We argue that improvements in the fabrication protocols as, for example, the use of a substrate free of dangling bonds are likely to produce WSe2-based FETs displaying higher room temperature mobilities, i.e. approaching those of p-doped Si, which would make it a suitable candidate for high performance opto-electronics.

Phototransistor Properties of Indium Tin Oxide Nanowires Grown by RF Sputtering Mechanism and Annealing Process

Photoconducting properties of indium tin oxide (ITO) nanowires grown by RF sputtering associated with annealing process were studied. ITO nanowires have been grown without the use of catalysts or oblique deposition. The cubic cross-sectional nanowires length was of the order of several microns, while their diameter was ~150–250 nm. The photoluminescence (PL) analysis on nanowires proved their excellent photoemission characteristics. Devices based on ITO nanowires showed a substantial increase in conductance of up to three orders of magnitude upon exposure to UV light and showing reproducible UV photoresponse and remaining relatively stable. The rising speed is slightly reduced, while the decay time is prolonged. Such devices also exhibited short response times and significant shifts in the threshold gate voltage. It was found that the dynamic response of the ITO nanowires phototransistor was stable with an on/off current contrast ratio of around 101. It is thus found that the change in the carrier concentrations in constant gate voltage was enhanced by 1.12 × 1017 cm-3 for the 350 nm UV light, corresponding to threshold-voltage shifts of before to after UV-light exposition. The photoconductive gain corresponding to responsivity measured at 350 nm was 0.11 × 105.

Radiation effects on the low frequency noise in partially depleted silicon on insulator transistors

The transfer characteristics and low-frequency noise behavior of partially depleted silicon on insulator n-channel metal-oxide-semiconductor transistors after γ-ray irradiation up to a total dose of 1M rad (Si) have been investigated in this paper. Due to the radiation-induced positive buried-oxide trapped charges and the interface traps, the back gate threshold voltage decreases from 44.72 to 12.88 V, and the electron field effect on mobility decreases from 473.7 to 419.8 cm2/V·s; while the sub-threshold swing increases from 2.47 to 3.93 V/dec. Based on the measurements of sub-threshold swing and the back gate threshold voltage, the variations of extracted radiation-induced buried oxide trapped charge and interface trap densities, are about 2.36×1012 cm-2 and 5.33×1011 cm-2 respectively. In addition, the normalized back gate flat-band voltage noise power spectral density is a sensitive function of radiation-induced buried oxide trapped charges and interface traps, which increases from 7×10-10 V2·Hz-1 to 1.8×10- 9 V2·Hz-1. According to the carrier number fluctuation model, the extracted trap density near the interface between channel and buried oxide increases from 1.42×1017 to 3.66×1017 cm- 3·eV-1. By considering the tunneling attenuation coefficient of the electron wave function and the tunneling depth of the electron in the buried oxide, the spatial distribution of trapped charges in the buried oxide before and after radiation are calculated and discussed.

Low frequency noise behaviors in the partially depleted silicon-on-insulator device

Low frequency noise in the partially depleted silicon-on-insulator (SOI) NMOS device is investigated in this paper. The experimental results show low frequency noise behaviors are in good consistence with classical noise model. Based on McWhorter model, the low frequency noise in the SOI device results from the exchange of carriers between channel and oxide. The densities of trapped charges in the front gate oxide and buried oxide are extracted. Due to the difference between manufacture processes, the extracted density of trapped charges in the buried oxide (Nt=8×1017 eV-1·cm-3) is larger than that in the gate oxide (Nt=2.767×1017 eV-1·cm-3), and the result is in good agreement with testing result of transfer characteristics in part 2. Based on the charge tunneling mechanism, the spatial distribution of trapped charges in the gate oxide and buried oxide are extracted by using the tunneling attenuation coefficient (λ=0.1 nm for SiO2) and time constant (τ0=10-10 s), and the result also proves that the trap in buried oxide is larger than that in gate oxide. In addition, the influence of channel length on the low frequency noise in the SOI device is discussed. The variations of normalized channel current noise power spectral density with channel length are investigated at four frequencies(10 Hz, 25 Hz, 50 Hz, and 100 Hz). The experimental results show that the normalized noise power spectral density decreases linearly with the increase of channel length, which indicates the low frequency noise of SOI device is mainly caused by the flicker noise in the channel, and the contribution of source/drain contact and parasitic resistances could be ignored. Finally, the dependences of back gate voltage on the front gate threshold voltage, front channel current and front channel noise are discussed by considering the charge coupling effect. The experimental results show the measured channel current and channel noise with applying front gate voltage and back gate voltage simultaneously are larger than those with applying the front gate voltage and back gate voltage separately.

Electronic structures of carbon nanotubes with monovacancy under an electric field

We report the electronic properties of carbon nanotubes (CNTs) with monovacancy under an electric field, based on density functional theory. The threshold gate voltage required to accumulate electrons and holes strongly depend on the relative positions of the defects on the CNTs, with respect to the electrode. Additionally, the defects induce an internal electric field in the nanotubes, causing the the threshold gate voltage variation for the carrier accumulation. Furthermore, the defects cause the field to concentrate around them.

Hysteresis and threshold switching characteristics in thin-film-transistors with inserted Pt-Fe2O3 core–shell nanocrystals

Hysteresis and threshold switching characteristics were investigated in the indium-gallium-zinc-oxide (IGZO) thin-film-transistors (TFTs) with inserted Pt-Fe2O3 core–shell nanocrystals (NCs) layer between source/drain and IGZO channel. The output curves showed the hysteresis with threshold drain voltage and the transfer curves showed the hysteresis with the shift of threshold gate voltage. These hysteresis, threshold switching, and shift of threshold voltage in both output and transfer curves are caused by charging of inserted NCs. These unique features demonstrated the memory and on/off switching operation by controlling both threshold gate and drain voltages through charging NCs.

Effect of antimony doping on the low-temperature performance of solution-processed indium oxide thin film transistors

The effects of antimony (Sb) doping on solution-processed indium oxide (InOx) thin film transistors (TFTs) were examined. The Sb-doped InSbO TFT exhibited a high mobility, low gate swing, threshold voltage, and high ION/OFF ratio of 4.6 cm2/V s, 0.29 V/decade, 1.9 V, and 3 × 107, respectively. The gate bias and photobias stability of the InSbO TFTs were also improved by Sb doping compared to those of InOx TFTs. This improvement was attributed to the reduction of oxygen-related defects and/or the existence of the lone-pair s-electron of Sb3+ in amorphous InSbO films. (© 2014 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim)

High photosensitivity few-layered MoSe2 back-gated field-effect phototransistors

In this paper, we report on the fabrication and optoelectronic properties of high sensitive phototransistors based on few-layered MoSe2 back-gated field-effect transistors, with a mobility of 19.7 cm2 V−1 s−1 at room temperature. We obtained an ultrahigh photoresponsivity of 97.1 AW−1 and an external quantum efficiency (EQE) of 22 666% using 532 nm laser excitation at room temperature. The photoresponsivity was improved near the threshold gate voltage; however, the selection of the silicon dioxide as a gate oxide represents a limiting factor in the ultimate performance. Thanks to their high photoresponsivity and external quantum efficiency, the few-layered MoSe2-based devices are promising for photoelectronic applications.

Pixel Level Characterization of Pinned Photodiode and Transfer Gate Physical Parameters in CMOS Image Sensors

A method to extract the pinned photodiode (PPD) physical parameters inside a CMOS image sensor pixel array is presented. The proposed technique is based on the Tan et al. pinning voltage characteristic. This pixel device characterization can be performed directly at the solid-state circuit output without the need of any external test structure. The presented study analyzes the different injection mechanisms involved in the different regimes of the characteristic. It is demonstrated that in addition to the pinning voltage, this fast measurement can be used to retrieve the PPD capacitance, the pixel equilibrium full well capacity, and both the transfer gate threshold voltage and its channel potential at a given gate voltage. An alternative approach is also proposed to extract an objective pinning voltage value from this measurement.

The Key Parameter Modeling of SiC MOSFET

This thesis mainly analysed the internal relations between parameters of SiC MOSFET and its dynamic and static characteristics respectively. And furthermore, a new method for modeling of SiC MOSFET based on PSpice was proposed in this paper. By introducing voltage’s controlling for voltage source E, we can compensate and correct the difference between PSpice default value of gate threshold voltage and actual value. At the same time, we can adopt two different junction capacitance models to describe the changes of junction capacitance which were brought about by the difference of the terminal voltage. In the meanwhile, there are newly increased source-drain resistance of MOSFET and gate resistance with the temperature change of variable temperature sub models. New models are able to fully and accurately reflect SiC MOSFET’s static and dynamic characteristics. Moreover, it provides an important foundation for switch process analysis of SC MOSFET, loss calculation and main circuit design. The fact that the experimental testing result is highly coincident with the simulation results verifies the correctness and accuracy of the models.

Effects of Ga:N addition on the electrical performance of zinc tin oxide thin film transistor by solution-processing.

This paper addressed the effect of gallium nitrate hydrate addition on thin film transistor (TFT) performance and positive bias stability of amorphous zinc tin oxide (ZTO) TFTs by solution processing, Further, the mechanisms responsible for chemical properties and electronic band structure are explored. A broad exothermic peak accompanied by weight loss appeared in the range from about 350 to 570 °C for the ZTO solution; the thermal reaction of the Ga-ZTO:N solution was completed at 520 °C. This is because the gallium nitrate hydrate precursor promoted the decomposition and dehydroxylation reaction for Zn(CH3COO)2·2H2O and/or SnCl2·2H2O precursors. The concentrations of carbon and chloride in gallium nitrate hydrate added ZTO films annealed at 400 °C have a lower value (C 0.65, Cl 0.65 at. %) compared with those of ZTO films (C 3.15, Cl 0.82 at. %). Absorption bands at 416, 1550, and 1350 cm(-1) for GaZTO:N films indicated the presence of ZnGa2O4, N-H, and N═O groups by Fourier transform infrared spectroscopy measurement, respectively. As a result, an inverted staggered Ga-ZTO:N TFT exhibited a mobility of 4.84 cm(2) V(-1) s(-1) in the saturation region, a subthreshold swing of 0.35 V/decade, and a threshold gate voltage (Vth) of 0.04 V. In addition, the instability of Vth values of the ZTO TFTs under positive bias stress conditions was suppressed by adding Ga and N from 13.6 to 3.17 V, which caused a reduction in the oxygen-related defects located near the conduction band.

Modeling the Response of the ESAPMOS4 RADFETs for the ALPHASAT CTTB Experiment

The Component Technology Test-Bed (CTTB) is one of the main components of the ALPHASAT spacecraft radiation Environment and Effects Facility (AEEF), an European Space Agency (ESA) Technology Demonstration Payload. In-flight data collected by the CTTB experiments will be used to validate ground test protocols, perform prediction models for new component technologies and to provide in-flight evaluation of critical component technologies for use in future missions. The relation between the RADFETs gate threshold voltage shift and the dose can strongly depend on the production processes parameters and needs to be experimentally determined before its use in space. A calibration test campaign of ESAPMOS4 RADFETs was conducted at the ESA/ESTEC Cobalt-60 facility. Irradiation runs were performed at three nominal temperatures: room temperature, 60°C, and 80°C. After the irradiation runs, the units underwent annealing, under similar temperature and bias configuration settings. A model capable of describing the RADFET temperature dependent response during irradiation, at low and high dose rate regimes, is presented in this paper, along with the analysis of the RADFET response during isothermal annealing, following irradiation.

Low-frequency noise in amorphous indium–gallium–zinc oxide thin-film transistors with an inverse staggered structure and an SiO2 gate insulator

We report the low-frequency noise (LFN) behavior of amorphous indium–gallium–zinc oxide thin-film transistors with an inverse staggered structure and an SiO2 gate insulator. The normalized noise power spectral density depended on channel length, L, with the form 1/L2, and on the gate bias voltage, VG, and threshold voltage, VTH, with the form 1/(VG − VTH)β where 1.5 < β < 2.1. In addition, the scattering constant α was less than 105 Ω. These results suggest that the contact resistance has a significant role in the LFN behavior and the charge-carrier density fluctuation is the dominant origin of LFN.

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness MOSFETs have been developed based on the minimum value of the front and back surface potentials. The threshold voltage and ideality factor models of the front and back gates have been verified with numerical simulations in terms of the device geometry parameters and the applied bias voltages, as well as with experimental results for devices with channel length down to 17 nm. Good agreement between the model, simulation, and experimental results were obtained by calibrating the minimum carrier charge density adequate to achieve the turn-on condition.

Investigating the degradation mechanisms caused by the TID effects in 130 nm PDSOI I/O NMOS

This paper evaluates the radiation responses of 3.3V I/O NMOSFETs from 130nm partially-depleted silicon-on-insulator (PDSOI) technology. The data obtained from 60Co ionizing radiation experiments indicate that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide, should be the dominant contributor to the off-state drain-to-source leakage current under ON bias. The body doping profile and device dimension are two key factors affecting the performance degradation of the PDSOI transistors after radiation. Significant front gate threshold voltage shift is observed in the T-shape gate device, which is well known as the Radiation Induced Narrow Channel Effect (RINCE). The charge trapped in the buried oxide can induce large threshold voltage shift in the front gate transistor through coupling effect in the low body doping device. The coupling effect is evaluated through three-dimensional simulation. A degradation of the carrier mobility which relates to shallow trench isolation (STI) oxide trapped charge in the narrow channel device is also discussed.

Double-gate tunnel field-effect transistor: Gate threshold voltage modeling and extraction

The tunnel field-effect transistor (TFET) is a potential candidate for the post-CMOS era. As one of the most important electrical parameters of a device, double gate TFET (DG-TFET) gate threshold voltage was studied. First, a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported. Then, a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film. The model as a function of the drain voltage, the Si layer thickness, the gate length and the gate dielectric was discussed. It is shown that the proposed model is consistent with the simulation results. This model should be useful for further investigation of performance of circuits containing TFETs.

Schottky barrier diode embedded AlGaN/GaN switching transistor

We developed a Schottky barrier diode (SBD) embedded AlGaN/GaN switching transistor to allow negative current flow during off-state condition. An SBD was embedded in a recessed normally-off AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistor (MOSHFET). The fabricated device exhibited normally-off characteristics with a gate threshold voltage of 2.8 V, a diode turn-on voltage of 1.2 V, and a breakdown voltage of 849 V for the anode-to-drain distance of 8 µm. An on-resistance of 2.66 mΩcm2 was achieved at a gate voltage of 16 V in the forward transistor mode. Eliminating the need for an external diode, the SBD embedded switching transistor has advantages of significant reduction in parasitic inductance and chip area.

Enhanced Radiation Sensitivity in Short-Channel Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors

The total ionizing dose effects of partially depleted silicon-on-insulator (SOI) transistors in a 0.13 μm technology are studied by 60Co γ-ray irradiation. Radiation enhanced drain-induced barrier lowering (DIBL) under different bias conditions is related to the parasitic bipolar in the SOI transistor and oxide trapped charge in the buried oxide, and it is experimentally observed for short channel transistors. The enhanced DIBL effect manifests as the DIBL parameter increases with total dose. Body doping concentration is a key factor affecting the total ionizing dose effect of the transistor. The low body doping transistor exhibits not only significant front gate threshold voltage shift as a result of the coupling effect, but also great off-state leakage at high drain voltage due to the enhanced DIBL effect.

Advanced Low-Voltage Power MOSFET Technology for Power Supply in Package Applications

In this paper, a high-current dc-dc power supply in package is reported with an emphasis on the design aspects of the low- and high-side power MOSFETs embedded in the power module. A new NexFET structure with its source electrode on the bottom side of the die (source down) is designed to enable an innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. A gate voltage pulldown circuitry monolithically integrated in the low-side NexFET is introduced to effectively prevent shoot-through faults even when a very low gate threshold voltage is used to reduce conduction and body diode reverse-recovery-related power losses. In addition, an asymmetric gate resistor circuitry is monolithically integrated in the high-side NexFET to minimize voltage ringing at the switch node. With all these novel device technology improvements, the new power supply in package module delivers a significant improvement in efficiency and offers an excellent solution for future high-frequency, high-current-density dc-dc converters.

Field-effect transistor based on ZnO nanorods with a variable threshold cutoff voltage

This study is concerned with the fabrication and electrical characteristics of short-channel (2 μm) field-effect transistors (FETs) based on ZnO nanorods. In FET fabrication, single-crystal ZnO nanorods are grown using the catalyst-free chemical vapor deposition (CVD) method. Although the short-channel ZnO-nanorod FETs exhibit good electrical characteristics (a transconductance of 100 nS, electron mobility of 6 cm2 V−1 s−1, and a large turn-ON/OFF ratio of 104), their characteristics significantly depend on the length of the nanorods. The effect of the drain-source voltage on the threshold gate voltage is studied.