Gate Structure Research Articles

Analysis of trapping effects on DC and RF performance in double Π-gate Al0.3Ga0.7N/GaN MOSHEMTs

Abstract This study investigates trap analysis of the DC and RF performance of Al0.3Ga0.7N/GaN Metal-Oxide-Semiconductor high electron mobility transistor (MOSHEMT) with double π-gate technology. The motivation behind double π-gate technology is to evenly distribute the peak electric field and reduce hot electron generation. This gate design helps to lower hot-electron generation across various operating conditions while maintaining device performance, particularly in the lower millimeter-wave frequency range. High dielectric constant HfO2 is used as gate oxide, which helps to lower the gate leakage current. Near the conduction band (CB), the electron quasi-fermi level of 30 meV is achieved. The practical application of HfO2 in AlGaN/GaN HEMTs is limited by its high oxygen permeability, brittleness, and reactivity with moisture and CO2, which can cause mechanical stress and form hafnium carbonate, adversely affecting device performance. Future designs of the double-π gate structure could enhance electrostatic control, reduce short-channel effects, and improve high-frequency performance by scaling down gate dimensions and using high-k or novel dielectric materials. Additionally, optimization for mm-wave and THz applications would help to maintain electron mobility and minimize parasitic capacitance and resistance.

Comprehensive study of Schottky-gated p-channel GaN field-effect transistors

In this work, a comprehensive study of Schottky-gated p-channel GaN field-effect transistors (GaN PFETs) with an energy-band modulated AlGaN barrier layer, a variable gate structure, and various densities of holes in the p-GaN layer is demonstrated to optimize electrical performance. The design rules for high-performance Schottky-gated GaN PFETs not only offer diverse pathways to achieve enhancement-mode operation but also improve output current density. Based on the design rules, a high-performance enhancement-mode GaN PFET with a high ION/IOFF ratio of 3 × 106, a low SS of 130 mV/dec, and a negative VTH of −1.09 V is fabricated, which is conducive to promoting the development of the low-power GaN complementary metal–oxide–semiconductor driving circuits.

Achieving Significant Multilevel Modulation in Superior-quality Organic Spin Valve.

Organic semiconductors, characterized by their exceptionally long spin relaxation times (≈ms) and unique spinterface effects, are considered game-changers in spintronics. However, achieving high-performance and wide-range tunable magnetoresistance (MR) in organic spintronic devices remains challenging, severely limiting the development of organic spintronics. This work combines straintronic multiferroic heterostructures with organic spin valve (OSV) to develop a three-terminal OSV device with a gate structure. The device exhibits a record-high MR ratio of 281% which 10 times higher than the average in polymer systems. More importantly, this work can perform multilevel writing operations on the device using gate voltages and create at least 10 stable spin-dependent working states within a single device. Both experiments and theoretical calculations confirm such an extraordinary tunability range originates from the synergistic effects of strain and charge accumulation that amplified by the spinterface. This study demonstrates the potential of OSV systems for efficient spin manipulation and highlights the spinterface as an ideal platform for amplifying spin effects for next-generation spintronic devices.

A study on turn-off, and on-resistance and short-circuit capability trade-off characteristics in 1.2-kV SiC MOSFETs

Abstract This paper presents experimental evaluations of the trade-off characteristics of the turn-off loss (E OFF) - slew rate of the drain current density (dJ D/dt) using the latest 1.2-kV SiC trench and planar MOSFETs. It found that smaller reverse transfer capacitances (C rss) improved E OFF - dJ D/dt. This was because of the moderately low doping density of the n-drift layer and the optimally designed gate structures. Experimental and numerical explorations were also conducted to identify structures that improve on-resistance (R on, sp) - short-circuit capabilities (SCWT). The trench MOSFETs achieved suppressed peak drain current densities in the short-circuit state while keeping low R on, sp, indicating superior R on, sp - SCWT to planar MOSFETs. Furthermore, the trench MOSFETs with narrower and higher doping J-FET regions can improve the trade-off. In conclusion, trench MOSFETs with optimized J-FET regions exhibited superior R on, sp - SCWT trade-off characteristics while showing comparable E OFF - dJ D/dt to planar MOSFETs.

Gate Oxide Reliability in Silicon Carbide Planar and Trench Metal-Oxide-Semiconductor Field-Effect Transistors Under Positive and Negative Electric Field Stress

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (Vth) and gate leakage current (Igss) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in SiO2 caused by oxide electric field (Eox) stress affect the Vth of SiC MOSFETs. The saturation and turnaround behavior of the Vth shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The Igss under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of Vth shift and Igss under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests.

A computational approach to optimize the linearity in dual-gate InAlGaN/AlN/GaN HEMTs

Abstract This paper investigates the effect of the proposed dual gate structures in enhancing the linearity of InAlGaN/AlN/GaN high-electron-mobility transistors (HEMTs) using TCAD analysis. Through the comprehensive analysis of the dual gate structure with the additional gate placed between the gate–source (DG-GS) and gate–drain (DG-GD) regions, the impact on the linearity performance has been compared with that of a standard single gate (SG) structure. The dual gate configuration exhibits a flatter and broader transconductance (g m) profile than the SG configuration. The reduction in the third-order intermodulation levels is confirmed with the polynomial fitting method. The f T/f max of the DG-GS case is simulated to be 52/102 GHz, which shows that such configuration does not deteriorate the RF performance. Comprehensive simulations are carried out to study the device physics and assess the mechanism behind the linearity improvement. The large signal model has been developed to examine the large signal RF performance as well as linearity performance metrics. An improvement of 9.6 dB in the carrier-to-intermodulation (C/I) ratio and that of 2.4 degrees in the amplitude-to-phase modulation at 6 dB backoff from P sat have been observed as compared to the SG configuration. Such characteristics have evidenced that the optimized dual-gate configuration with the second gate placed between the source and gate can effectively improve the linearity performance of the InAlGaN/AlN/GaN HEMT configurations.

Speculative Heritage: Architectural Imagination as a Gateway to Alternative Futures for Iranians at Home and in the Diaspora

ABSTRACT This article focuses on the Azadi Tower, a prominent gate structure in Tehran, to discuss how an authoritarian monument has the potential to become a shared space of public discourse, both physically and visually. In so doing, it opens up a discussion of the construction of spatial imaginaries as a category of cultural heritage, specifically in geographies of conflict. Initially named Shahyad, the tower and the square around it were built in 1971 as a monument to the Shah. Despite the controversial genesis of the structure, it was given new meanings after the 1979 revolution and renamed Azadi (freedom) Tower. This article considers the centrality of the structure in the visual materials expressing dissent in the recent years in Iran and across the Iranian diaspora, and addresses the various stages of physical and visual re-invention of the structure since the 1979 revolution to comprehend its role as a speculative solidarity monument in contemporary Iran. In this sense, architectural heritage opens up new possibilities not just through its lived experiences, but also its yet-to-be-lived subjective imaginaries.

Improved breakdown voltage and dynamic Ron characteristics in normally-off GaN-based HEMTs featuring fully-recessed and bilayer-dielectric gate structure

Abstract The degradation of dynamic on-resistance (Ron) is a major challenge in GaN-based high electron mobility transistors (HEMTs), which seriously affects their performance and reliability. The degradation area of dynamic Ron mainly comes from two aspects. One is the region below the gate that also affects the threshold voltage (Vth) of the devices. And the other one is the interface region of the gate to drain access. The optimal device exhibits a Vth of 0.97 V, a small Vth hysteresis of only 20 mV, a high current density of 723 mA/mm, and a breakdown voltage (BV) of 760 V which could be further boosted when additional field plate design is employed. It is found that when high voltage drain stress is applied, a positive Vth shift is induced, leading to the decrease of the effective gate driving voltage, and thus the dynamic Ron of the devices is increased. Of particular concern is the effects of dielectric layer and/or interface of the access region on the dynamic Ron degradation, which can be alleviated by removing the dielectric layer of the access region.

Improved lateral figure-of-merit of heteroepitaxial α-Ga2O3 power MOSFET using ferroelectric AlScN gate stack

In this Letter, we demonstrate heteroepitaxial α-Ga2O3 MOSFETs using an aluminum scandium nitride (AlScN) ferroelectric gate stack. Owing to ferroelectric effects, α-Ga2O3 MOSFETs with the AlScN/HfO2 gate stack (FGFET) exhibited enhanced electrical performance compared with a HfO2 gate dielectric (IGFET) for variable gate–drain lengths (10, 15, 20 μm). A remnant polarization value of the AlScN deposited on a HfO2 layer was measured to be about 30 μC/cm2. The subthreshold swing (SS) and field-effect mobility (μFE) of IGFET was extracted at 1814 mV/dec and 13.9 cm2/V s, respectively. However, the FGFET exhibits a reduced SS of 552 mV/dec with enhanced μFE of 42.7 cm2/V s owing to the negative capacitance of the ferroelectric AlScN. Furthermore, a lateral figure-of-merit of 17.8 MW/cm2 was achieved for the FGFET, far surpassing the 8.3 MW/cm2 of the IGFET. The proposed ferroelectric AlScN/HfO2 stack can be a promising gate structure for improving both transfer and breakdown characteristics in heteroepitaxial α-Ga2O3 power devices.

New tile-based circuits converting BCD code to gray, excess-3, and aiken codes in quantum-dot cellular automata (QCA) nanotechnology

The development of new methods and technologies for improving the stability and reducing the power consumption of electronic devices is a crucial area of research. Quantum-dot Cellular Automata (QCA) has emerged as a promising alternative to the traditional Complementary Metal-Oxide-Semiconductor (CMOS) technology, offering superior optimization in terms of physical size and energy efficiency. This paper introduces three novel digital code converters, designed using the tile-based approach to simplify circuit implementation and enhance integration through optimized majority and inverter gate structures. The proposed converters include: (1) a BCD to gray code converter with 127 cells, 0.18 μm2 occupied area, 3 clock phases, and zero NOT gate achieving a 7.3 % and 100 % reduction in the number of cells and NOT gates, respectively, compared to the most similar design; (2) a BCD to excess-3 code converter with 190 cells, 0.25 μm2 occupied area, 7 clock phases, and 3 NOT gates, showing a 0.5 %, 13.8 %, 41.7 %, and 25 % reduction in cells, area, used clock phases, and NOT gates, respectively, compared to the closest alternative; and (3) a BCD to aiken (2421) code converter with 287 cells, 0.22 μm2 occupied area, zero NOT gate, and 5 clock phases. The energy dissipation for these converters is measured at 55.3 meV, 53.7 meV, and 102 meV, respectively. Simulations are performed using QCADesigner-E version 2.2, validating the functionality and performance of the designs. These results demonstrate the potential of the proposed converters to offer efficient, compact, and low-power solutions for digital systems.

Tunable two-photon THz emissions through pair annihilation in graphene with a double gate structure

How far the analogy between massless Dirac fermions in a truly relativistic (1+2)-D spacetime and electrons near the Fermi level in graphene can be seriously taken? A hallmark of relativistic QFT is the multi-photon emission through pair annihilation. In this paper, to address this question we formulate the theoretical basis for a double gate graphene device. In an infinite sheet of pristine graphene the Fermi level is located at the Dirac points, but it can be tunned through gate potentials. This way, electron and hole pockets are induced, forming N and P regions in a large monolayer graphene sheet. The quasi-particles can be accelerated through the source-drain potential to scatter at an intrinsic region, leading to electron-hole annihilation. Feynman amplitudes and emission rates for two-photon emissions arising from electron-hole annihilation in graphene are presented at lowest order, leading to analytical formulae for two photon production, which could experimentally be tested.

Subthreshold Drain Current Model of Cylindrical Gate All‐Around Junctionless Transistor With Three Different Gate Materials

ABSTRACTA novel subthreshold drain current model has been developed for a cylindrical gate all‐around junctionless transistor with three different gate materials. The proposed device is built with three gate regions of different work functions that effectively reduce the short‐channel effects caused by quantum mechanical effects. The drain current equation is solved for all three operating regions to investigate the device switching characteristics and minimize the drain‐induced barrier lowering (DIBL), velocity saturation, mobility degradation, and tunneling. It is understood that the triple material gate structure enhances the transport efficiency of the device. The proposed analytical model is validated by comparison with Sentaurus TCAD numerical simulator results and good agreement is found to be achieved.

Demonstration of aluminum nitride metal oxide semiconductor field effect transistor on sapphire substrate

Abstract Aluminum nitride (AlN) is a promising ultrawide bandgap material with significant advantages for power electronics and optoelectronic applications due to its high breakdown voltage, mobility, and thermal conductivity. AlN Schottky barrier diodes and metal semiconductor field effect transistors have shown potential but are limited by issues such as high off-state leakage current and complex structures to achieve ohmic contacts. To address these challenges, we report on the fabrication and characterization of an AlN metal oxide semiconductor field effect transistor (MOSFET) with a recessed gate structure. The source and drain contacts were fabricated on n-doped AlN epitaxy using Ti-based contacts with a Ti/Al/Ti/Au metal stack. To evaluate the performance of these contacts, a circular transmission line model was employed, and contacts were annealed at various temperatures ranging from 750 °C to 950 °C in a nitrogen ambient. Our results reveal that unannealed Ti-based contacts on AlN showed no current conduction. However, annealing these contacts at 950 °C for 30 s significantly reduced the specific contact resistance to 0.148 Ω·cm2, achieving an ∼80% reduction compared to samples annealed at 750 °C. Utilizing these optimized contact conditions, we fabricated, to the best of our knowledge, the first AlN MOSFET. The fabricated AlN MOSFET exhibits a threshold voltage of −10.91 V, an effective mobility of 2.95 cm2 V−1 s−1, an on–off current ratio spanning two orders of magnitude, and a reverse breakdown voltage of approximately ∼250 V in air without a field plate.

Numerical Simulation on the Impact of Back Gate Voltage in Thin Body and Thin Buried Oxide of Silicon on Insulator (SOI) MOSFETs

Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely, -2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.

Gated InAs quantum dots embedded in surface acoustic wave cavities for low-noise optomechanics.

Self-assembled InAs quantum dots (QDs) are promising optomechanical elements due to their excellent photonic properties and sensitivity to local strain fields. Microwave-frequency modulation of photons scattered from these efficient quantum emitters has been recently demonstrated using surface acoustic wave (SAW) cavities. However, for optimal performance, a gate structure is required to deterministically control the charge state and reduce the charge noise of the QDs. Here, we integrate gated QDs and SAW cavities using molecular beam epitaxy and nanofabrication. We demonstrate that with careful design of the substrate layer structure, integration of the two systems can be accomplished while retaining the optimal performance of each subsystem. These results mark a critical step toward efficient and low-noise optomechanical systems that truly leverage the excellent properties of semiconductor QDs.

Taguchi Method Statistical Analysis on Characterization and Optimization of 18-nm Double Gate MOSFETs

A bi-layer graphene with a multigate structure was intensified and analysed on an 18-nm Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) device to obtain an optimal performance parameter. The device has a gate structure made of Titanium Dioxide (TiO2) that serves as a high-k material and a metal gate made of Tungsten Silicide (WSix). The Silvaco TCAD Software which are ATHENA and ATLAS modules were used to enhance the fabrication process of virtual devices and to verify the electrical properties of a specific device. According to the International Technology Roadmap Semiconductor (ITRS) specifications of 0.179 V ± 12.7% for threshold voltage (VTH) and 20 nA/m for leakage current (ILEAK), the Taguchi L9 orthogonal array strategy was used to improve the device process parameters for optimum VTH and ILEAK. For the NMOS device, the process parameter of VTH Adjust Implant Dose was used as the dominant factor while Source/Drain (S/D) Implant Energy was used as the adjustment factor whereby for PMOS device, S/D Implant Energy was the dominant factor while S/D Implant Tilt was the adjustment factor in order to achieve a robust design through the Taguchi method implementation. The percentage affecting the process parameter is then applied to the results of the signal to noise ratio (SNR) of Nominal-the-best (NTB) for VTH and Smaller-the-better (STB) for ILEAK.

Design and Optimization of Water Level Control Gate System in Malwathu Oya River, Sri Lanka

This research focuses on improving flood management of the Malwathu Oya River in Anuradhapura Historical City, Sri Lanka, by designing an efficient gate system for the weir of Halpan Ela in the Malwathu Oya River. Frequent flooding threatens agriculture, infrastructure, and public safety in this region. This research aims to enhance water level control in the upper reach of Halpan Ela Anicut by evaluating rainfall patterns, tank spillway efficiency, and gate operation challenges. Historical data on rainfall and tank spillage were analyzed. Flow simulations revealed significant pressure differences, with the existing gate structure showing an upstream pressure of 114,492.5 Pa at a maximum flow of 1740 m3/s, compared to 105,406 Pa for the new flap gate system at the same flow rate. This represents a pressure difference of 9 kPa, equivalent to a 0.9 m water head. Despite the system’s estimated cost of USD 0.1 million, the potential reduction in river flood damage, which currently exceeds USD 0.2 million annually, demonstrates its value. This research emphasizes the effectiveness of the flap gate system in reducing flood risks in Anuradhapura City compared to the existing gate type, though it is only a part of a broader flood mitigation strategy.

Enhanced Threshold Voltage and Improved Subthreshold Swing Using NiOX/ITO Reverse Bias Gated Diamond pMOS

An increase in the device performance of diamond‐based p‐type metal–oxide–semiconductor (pMOS) transistors using a combination of p‐type nickel oxide and n‐type indium tin oxide (NiOX/ITO) reverse bias diode as the gate dielectric is reported. Negative threshold voltage pMOS transistors are desirable for digital circuits and power applications for fail‐safe operation. A Schottky gate‐based conventional diamond pMOS transistor suffers from many limitations, including a positive threshold voltage (VT). Herein, it is experimentally demonstrated that NiOX/ITO gate dielectric with Al gate contact circumvents many critical limitations, providing a negative threshold voltage of −1.2 V, improved subthreshold slope of 145 mV dec−1, current ON/OFF ratio >107, and peak gate leakage current reduction >103. An Al/NiOX‐based control gate structure shifts the VTH negative with improvements in crucial device performances. Adding a reverse bias junction through the Al/ITO/NiOX heterointerface with the Al metal gate further improves performance. The measured device characteristics are explained in a common framework of energy band diagram for all the devices.

Fabrication of InP Vertical Gate-All-Around Transistors Using Crystal Phase Transition Heterojunction

The crystal phase heterojunction (CPHJ) is essentially a new type of heterojunction without misfit dislocations and lattice relaxation. The transistor structure using the CPHJ could significantly impact the transistor technologies. However, CPHJ has difficulty in fabricating a gate structure that modulates the electric field normal to the the CPHJ. Here, we report on the selective-area growth of WZ-InP NWs for InP NWs and demonstration of vertical gate-all-around transistors using the InP CPHJ.

Enhanced Stability Under Positive Bias Temperature Stress in Oxide Thin Film Transistors with Double Gate Structure By Improving Bottom Channel Interface

In this paper, we discuss the causes of reliability degradation in oxide TFTs with a double gate structure and propose methods for improvement. Reducing IGZO deposition power significantly improves PBTS (Positive Bias Temperature Stability) reliability in double gate structures. This improvement is attributed to reduction of excess oxygen defects accumulated at the bottom channel interface, as inferred from the difference in PBTS results for the top single gate and double gate structures