Abstract
Abstract The degradation of dynamic on-resistance (Ron) is a major challenge in GaN-based high electron mobility transistors (HEMTs), which seriously affects their performance and reliability. The degradation area of dynamic Ron mainly comes from two aspects. One is the region below the gate that also affects the threshold voltage (Vth) of the devices. And the other one is the interface region of the gate to drain access. The optimal device exhibits a Vth of 0.97 V, a small Vth hysteresis of only 20 mV, a high current density of 723 mA/mm, and a breakdown voltage (BV) of 760 V which could be further boosted when additional field plate design is employed. It is found that when high voltage drain stress is applied, a positive Vth shift is induced, leading to the decrease of the effective gate driving voltage, and thus the dynamic Ron of the devices is increased. Of particular concern is the effects of dielectric layer and/or interface of the access region on the dynamic Ron degradation, which can be alleviated by removing the dielectric layer of the access region.
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