Gate Static Induction Transistors Research Articles

Stacked Assembly of SiC Cascode Using Buried Gate Static Induction Transistor

A 650-V and 10-A silicon carbide (SiC) stacked cascode assembly has been proposed and demonstrated, in which a low-voltage Si-MOSFET (LV Si-MOSFET) is stacked on a high-voltage SiC buried gate static induction transistor (HV SiC-BGSIT). This is achieved by mounting Al bumps on the source pad of the HV SiC-BGSIT die and inserting a stacked Ag paste/epoxy layer between the HV SiC-BGSIT die and LV Si-MOSFET die. The epoxy layer is used to electrically separate the wire bonded on the gate pad of the HV SiC-BGSIT from the bottom electrode of the LV Si-MOSFET. The results of the measured static characteristics at temperatures from room temperature to 400 K and hard switching characteristics at room temperature of the fabricated stacked cascode sample verify that the proposed stacked cascode assembly successfully performs as a SiC cascode switching device. Thus, the proposed assembly contributes to the reduction in the footprint and parasitics for the conventional discrete packages and modules using the SiC cascode configuration.

Stress Test of Cascode Switch Using SiC Static Induction Transistor

Stress tests were conducted for the cascode switch using the SiC buried gate static induction transistor (SiC-BGSIT). The stress of the reverse overshoot voltage was periodically applied to the pn junction between the gate terminal and source one in the BGSIT in the cascode with pulses of 40kHz for 202 hours. This simulates the stress which can be occurred in the channel region of the BGSIT during the turn-off and turn-on operation with a parasitic inductance in the interconnection of the cascode package. The result of the stress tests has revealed that there is no significant difference between the electrical characteristics of the BGSIT cascode sample before the stress and those after the stress. Thus, the BGSIT cascode can guarantee high reliability against the stress. The result from the drain current DLTS suggests that no deferent kind of defect is created in the channel region of the BGSIT by the stress.

Extremely Low ON-Resistance SiC Cascode Configuration Using Buried-Gate Static Induction Transistor

A 35-A cascode configuration of a drain-to-source breakdown voltage of 978 V utilizing an silicon carbide (SiC) buried gate static induction transistor (BGSIT) and low voltage Si-MOSFET (SiC-BGSIT cascode) has been experimentally demonstrated for the first time. The SiC-SIT is mounted with the Si-MOSFET in an originally designed resin 4pin package. The ON-resistance $R_{\text {DS(ON)}}$ of this device exhibits 34.3 $\text{m}\Omega $ at room temperature, which is 50% of the commercial SiC MOSFET of the similar rating. The temperature dependence of $R_{\text {DS(ON)}}$ and gate threshold voltage has been revealed. It has been suggested that when compared with the SiC-JFET cascode with the similar rating, the BGSIT cascode has a soft $\textit {dV}_{\text {ds}}/\textit {dt}$ property with a relatively small switching loss.

Cascode Configuration of SiC-BGSIT and Si-MOSFET with Low On-Resistance and High Transconductance

We investigate a cascode configuration of a normally-on SiC-Buried Gate Static Induction Transistor (SiC-BGSIT) and Si-MOSFET as an alternative switching device of the SiC-MOSFET. It is shown that the transconductance of our cascode device is much higher than that of commercial SiC-MOSFETs while the switching speed is much faster than that of normally-off SiC-BGSITs. The origin of the fast switching speed in this cascode configuration is discussed in terms of a simulated reverse transfer capacitance.

3 kV Normally-Off 4H-SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm2, compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm2.

Experimental Study of Short-Circuit Capability of Normally-off SiC-BGSITs

We investigated the short-circuit capabilities of 1.2 kV normally-off SiC buried gate static induction transistors (SiC-BGSITs). The maximum short-circuit energy was found to be 35.6 J/cm2, which is twice that of normally-on SiC-BGSITs and 3.3–5.6 times higher than that of the Si-IGBTs. The maximum short-circuit time was 590 μs. It is concluded that these high short-circuit capabilities result from saturation characteristics of the normally-off SiC-BGSITs.

980 V, 33A Normally-Off 4H-SiC Buried Gate Static Induction Transistors

In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.

Radiation Hardness Evaluation of SiC-BGSIT

In this study, we evaluated the radiation hardness of SiC Buried Gate Static Induction Transistors (SiC-BGSITs) and Si-based switching devices up to the absorbed dose of 10 MGy(SiO2). The on-voltage Von of Si-IGBT degraded excessively at the early stage of the irradiation (>~0.1 MGy(SiO2)) due to the bulk damage produced by Compton electrons like the gain degradation in Si bipolar transistors. The threshold voltage Vth of Si-MOSFET was very sensitive against the radiation due to the competing mechanism between the generation of the hole traps in the gate SiO2 and the SiO2/Si interface states. Moreover, the breakdown voltage VBR and leak current Ileak of MOSFET degraded significantly against the absorbed dose. While, the electrical properties of SiC-BGSIT was very stable even after the irradiation of 10 MGy(SiO2).

Crystalline Quality of Channel Regions in SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

We investigated the crystalline quality and electrical properties of the channel regions in 4H-SiC buried gate static induction transistors (SiC-BGSITs). To accurately determine the characteristics of the channel regions, we performed transmission electron microscopy and scanning spreading resistance microscopy. It was found that the channel regions have high crystalline quality and no significant fluctuations in doping concentration.

Evaluation of Refilled Channel Regions in 4H-SiC Buried Gate Static Induction Transistors

We evaluated the crystalline quality of the channel region in silicon carbide buried gate static induction transistors (SiC-BGSITs) by transmission electron microscopy (TEM) and scanning spreading resistance microscopy (SSRM). TEM observations revealed that no crystalline defects were generated in the channel region of SiC-BGSITs during epitaxial regrowth in trenches. The SSRM result indicated that the refilled channel region had a spreading resistance distribution of about ten times due to a high noise resulting from contact resistance. This noise was so high that we could not detect carrier density distributions from SSRM signals. However, on the basis of the leakage current and blocking characteristics of the SiC-BGSITs, we confirmed that there was no serious carrier density distribution that affected the device operation in the channel region.

Short-Circuit Operation of SiC Buried Gate Static Induction Transistors (SiC BGSITs)

Short-circuit capabilities of silicon carbide static induction transistors with the buried gate structures (BGSITs) have been measured for the first time, and have been followed by 2D device simulations. The short-circuit operation of the normally-on type BGSITs is characterized by an abrupt decrease in the output current through a high peak in the initial phase of the short-circuit period, which is distinguished from that of the conventional IGBTs and power MOSFETs. This operation is caused by the inherent operation of the SITs including the non-saturating current-voltage characteristics with the unipolar operation. Decreasing the channel width adequately is a useful method to increase the short-circuit capability.

Silicon Carbide Static Induction Transistor with Implanted Buried Gate

Buried gate static induction transistors (BGSITs) were fabricated on commercial 4H-SiC wafer with 20 m thick n-type epilayer having a net donor density of 0.71015 cm-3. Buried gate regions were formed by the selective implantation of high energy (up to 2 MeV) aluminium performed at 600 °C. Nitrogen was implanted at temperature of 400 °C to form a heavily doped blanket source region. Post-implantation annealing was carried out at the atmospheric pressure in argon using a graphite capping layer. Fabricated normally-on devices with source contact diameter of 0.2 mm were tested at temperatures up to 500 °C and current densities up to 270 A/cm2. The specific on-resistance of a completely open 4H-SiC BGSIT was 34 mcm2 and showed a thermally activated behaviour at temperatures up to 500 °C.

Three Dimensional Analysis of Turnoff Operation of SiC Buried Gate Static Induction Transistors (BG-SITs)

The turnoff mechanism of SiC buried gate static induction transistors (SiC-BGSITs) were analyzed by three dimensional device simulation. A current crowding occurs in the portion near the channel center away from the gate contact during the initial phase of the turnoff operation, which is resulted from a non-uniform potential distribution through the gate finger with the displacement current flowing there. This increases the turnoff delay time. The impact of source length on the turnoff performance was made clear.

1270V, 1.21mΩ·cm<sup>2</sup> SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.

Low temperature operation of UHF power static induction transistors

This paper describes the results of recent experiments with high power surface gate static induction transistors (SITs) operated at and near liquid nitrogen temperatures. The temperature dependence of important large signal and small signal device parameters over a wide range of operating temperatures is described. UHF power performance of liquid nitrogen cooled SIT power amplifiers is described as well. At 425 MHz, a single transistor power amplifier has been fabricated which exhibits output power levels > 350 W with 8 dB gain and nearly 80% drain efficiency. Smaller test devices have been used in an 850 MHz amplifier, which exhibits 30 W c.w. with 7.8 dB gain and 64% drain efficiency.

Bipolar Mode Static Induction Transistor

Junction gate static induction transistor (JSIT) is designed as normally-off device, where the channel is completely pinched-off by the gate to channel built-in voltage, thus establishing a potential barrier in the channel. An application of forward gate bias voltage lowers the potential barrier and allows the drain current to flow. This normally-off JSIT is called bipolar mode SIT (BSIT). Basic characteristics of BSIT is similar to that of bipolar transistor. BSIT is characterized by low impedance, high current gain, high transconductance and high current density, so that BSIT is promising for high current, high speed and high efficiency switching devices as well as low voltage and low energy integrated circuits. Basic operational principle of BSIT is described by feedback theory with a consideration to the virtual base resistance.