Extremely Low ON-Resistance SiC Cascode Configuration Using Buried-Gate Static Induction Transistor

Abstract

A 35-A cascode configuration of a drain-to-source breakdown voltage of 978 V utilizing an silicon carbide (SiC) buried gate static induction transistor (BGSIT) and low voltage Si-MOSFET (SiC-BGSIT cascode) has been experimentally demonstrated for the first time. The SiC-SIT is mounted with the Si-MOSFET in an originally designed resin 4pin package. The ON-resistance $R_{\text {DS(ON)}}$ of this device exhibits 34.3 $\text{m}\Omega $ at room temperature, which is 50% of the commercial SiC MOSFET of the similar rating. The temperature dependence of $R_{\text {DS(ON)}}$ and gate threshold voltage has been revealed. It has been suggested that when compared with the SiC-JFET cascode with the similar rating, the BGSIT cascode has a soft $\textit {dV}_{\text {ds}}/\textit {dt}$ property with a relatively small switching loss.