Gate-source Bias Research Articles

Mechanism of Superior Suppression Effect on Gate Current Leakage in Ultrathin Al2O3/Si3N4 Bilayer-Based AlGaN/GaN Insulated Gate Heterostructure Field-Effect Transistors

On the basis of the thin barrier surface (TSB) model, the mechanism of gate current leakage under reverse gate–source bias in nitride-based heterostructure field effect transistors (HFETs) and metal–insulator–semiconductor (MIS) HFETs with an ultrathin (1 nm/0.5 nm) Al2O3/Si3N4 bilayer has been investigated. The simulations show that the electron tunneling through the Schottky barrier is the dominant mechanism for gate current in conventional HFETs due to the high density of donor like defects on the surface. An Al2O3/Si3N4 bilayer insulator can substantially reduce the donor like surface defect density and then significantly suppress the gate current leakage in nitrides-base MIS-HFET devices.

Method for Predicting<tex>$f_T$</tex>for Carbon Nanotube FETs

A method based on a generic small-signal equivalent circuit for field-effect transistors is proposed for predicting the unity-current-gain frequency f/sub T/ for carbon-nanotube devices. The key to the useful implementation of the method is the rigorous estimation of the values for the components of the equivalent circuit. This is achieved by numerical differentiation of the charges and currents resulting from self-consistent solutions to the equations of Schrodinger and Poisson. Sample results are presented, which show that f/sub T/ can have a very unusual dependence on the gate-source bias voltage. This behavior is due mainly to the voltage dependence of the transconductance and capacitance in the presence of quasi-bound states in the nanotube.

GaAs-based metal-oxide semiconductor field-effect transistors with Al2O3 gate dielectrics grown by atomic layer deposition

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al2O3 gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al2O3 possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (fT) of 14 GHz and a maximum oscillation frequency (fmax) of 25.2 GHz have been achieved from a 0.65-µm gate-length device. The interface trap density (Dit) of Al2O3/GaAs is evaluated by the hysteresis of drain-source current, Ids, versus gate-source bias, Vgs, and the frequency dispersion of transconductance, gm.

Reduction of Effect due to Parasitics in Integrated Wave Filters

Design of integrated wave filters with effect due to parasitics relaxed is proposed. Improvement of frequency characteristics is achieved by using current-mode circuits and appropriately transforming the transfer function of a wave unit. Circuitry of two building blocks one of which follows another in a wave filter is also simplified for eliminating parasitics. Moreover small-signal analysis leads to a design guidance that the gate-source bias voltage of a MOSFET which operates as an equivalent resistor should be large. Two wave filters are designed based on the guidance as examples and validity of the guidance is verified with SPICE.

Bias Dependent Subband Edges and the 0.7 Conductance Anomaly

The 0.7 (2e2/h) conductance anomaly is studied in strongly confined, etched GaAs/GaAlAs quantum point contacts by measuring the differential conductance G as a function of source-drain bias Vsd and gate-source bias Vgs as well as a function of temperature. In the Vgs- Vsd plane we use a grayscale plot of the transconductance dG/dVgs to map out the bias dependent transitions between the normal and anomalous conductance plateaus. Any given transition is interpreted as arising when the bias controlled chemical potential μd (μs) of the drain (source) reservoir crosses a subband edge εα in the point contact. From the grayscale plot we extract the constant normal subband edges ε0, ε1,... and most notably the bias dependent anomalous subband edge ε'0 (μd) split off from ε0. We show by applying a finite-bias version of the recently proposed BCF model, how the bias dependence of the anomalous subband edge is the key to analyze various experimental observations related to the 0.7 anomaly.

SiO2 / Gd2 O 3 / GaN Metal Oxide Semiconductor Field Effect Transistors

GaN-based metal oxide semiconductor field effect transistors (MOSFETs) were demonstrated using a stacked gate oxide consisting of single-crystal and amorphous provides a good oxide/semiconductor interface and reduces the gate leakage current and enhances oxide breakdown voltage. Charge modulation of the n-channel depletion mode MOSFET was achieved for gate voltage from +2 to −4 V. The source-drain breakdown voltage exceeded 80 V. An intrinsic transconductance of 61 mS/mm was obtained at a gate-source and drain-source bias of −0.5 and 20 V, respectively. This is the first demonstration of epitaxial growth on GaN and the first use of as an insulating layer for nitride electronic device applications. © 2001 The Electrochemical Society. All rights reserved.

Transient characteristics of AlxGa1−xN/GaN heterojunction field-effect transistors

Transient characteristics of drain-source current in response to picosecond pulsed gate-source voltages in AlxGa1−xN/GaN heterojunction field-effect transistors (HFETs) have been measured. It was found that the switching time constants were of the order of tens of picoseconds and depended strongly on the gate-source bias VGS as well as drain-source bias VDS. Slow transients caused by charge trapping effects such as those observed in AlGaAs/GaAs HFETs were absent in AlGaN/GaN HFETs. Our results suggested that the dependence of the effective electron mobility on the sheet density dictates the overall drain current transient characteristics as well as the device switching speed of AlGaN/GaN HFETs.

Analytic modeling of the subthreshold behavior in MOSFET

An analytic model is derived to describe the bias-dependent behavior of the subthreshold swing in MOSFETs for the uniform channel and the ion-implanted channel, and is compared to two-dimensional simulation, Tsividis’ model and Brews’ model. This simple analytical model confirms that the subthreshold swing is a function of the gate–source bias and exhibits a global minimum in the weak inversion region. This model is based on Tsividis’ current equations and assumes that the surface potential difference between the drain and the source is small for the gate–source voltage below the threshold voltage. This yields a conventional exponential form of the subthreshold current, and the subthreshold swing can be obtained analytically from this current equation.

Hot electron degradation effects in 0.14 μm AlInAs/GaInAs/InP HEMTs

We report on hot electron stress measurements on 0.14 μm MOCVD grown AlInAs/GaInAs/InP HEMTs. The stress measurements increase the drain-source current and hence induce a temporary negative shift in the threshold voltage in unpassivated HEMTs. A permanent negative shift in the threshold voltage has been obtained in passivated HEMTs. The observed degradation (temporary/permanent) is due to the storage of positive charges (created by the impact ionization in the channel) in the Schottky AlInAs layer (temporary) or at the interface of semiconductor-passivation layer (permanent). For a given drain-source bias, a shift in the threshold voltage is larger in the gate-source bias region where the device has a maximum transconductance value.

An FET-level linearization method using a predistortion branch FET

To reduce third-order intermodulation distortion (IMD3), a linearization circuit using a predistortion branch field-effect transistor (FET) was proposed and its performance was verified for a hybrid circuit. The method is based on the fact that IMD3 generated from main FET is nulled by that from a branch FET with optimized bias condition. For two-tone frequencies 900 and 904 MHz, the performance of the circuit showed up to 13.9 dB improvement in the output third-order intermodulation intercept point (OIP3) at its peak point and more than 6.3 dB for 0.2 V range of branch FETs gate-source bias. For its simple topology and improvement in OIP3, the method merits use in monolithic microwave integrated circuit (MMIC) amplifiers for low-to-medium power applications.

Light emission from tunnelling mode GaAs static induction transistor

Vertical type GaAs static induction transistors (SIT) with 160 Å channels were fabricated with selective regrowth, using molecular layer epitaxy. The structure with a sidewall channel is suitable for electron transport investigation with electroluminescence spectra. The room temperature spectra (below bandgap, in the range from 0.6 eV to 1.4 eV) indicate tunnelling as the room temperature electron transport mechanism for this device. At sufficiently high drain–source or gate–source bias voltages, most of the electrons are injected directly from the source to the drain. The electron transit time was roughly estimated as 2 × 10–14 s.

A physical interpretation for the single-event-gate-rupture cross-section of n-channel power MOSFETs

The single-event-gate-rupture cross-section is measured as a function of drain-source and gate-source bias for some n-channel power MOSFETs. The experimental techniques are explained, and the results are interpreted with the help of two-dimensional computer modeling.

Fabrication and characterization of a depletion-mode ZnS/sub 0.07/Se/sub 0.93/ MESFET

We report the fabrication and characterization of a depletion-mode n-channel ZnS/sub 0.07/Se/sub 0.93/ metal-semiconductor field effect transistor (MESFET). A ZnSSe FET could be a key element in opto-electronic integration consisting of light emitters, light receivers and MESFET pre-amplifiers. Mesa isolation, recess etching and self-alignment techniques were adopted to optimize the MESFET performance. Source and drain (S/D) ohmic contacts and gate Schottky contact were formed by Cr/In/Cr and Au deposition, respectively. Depletion mode FET's with varying gate width-to-length ratio of W/L=200 /spl mu/m/20 /spl mu/m, 200 /spl mu/m/4 /spl mu/m and 200 /spl mu/m/2 /spl mu/m were fabricated. A 2 /spl mu/m FET was characterized as follows: the turn-on voltage, V/sub on//spl ap/1.75 V, the pinch-off voltage, V/sub p//spl ap/-13 V, the unit transconductance, g/sub m//spl ap/8.73 mS/mm, and the breakdown voltage with zero gate-source bias, BV/spl ap/28 V.

Influence Of The Density of States and Series Resistance on the Field-Effect Activation Energy in a-Si:H TFT

AbstractWe have proposed a new two-dimensional simulation model, which takes into account the density of states of hydrogenated amorphous silicon (a-Si:H) and temperature-dependence of the source/drain series resistances (Rs), to explain the dependence of the activation energy (Eact) of drain-source current (IDs) on gate-source bias (VGs) in a-Si:H thin-film transistors (TFTs). We found that the influence of series resistance cannot be ignored, else an overestimated Eact will result. The results of our simulation are in agreement with experimentally observed saturation of the Eact at higher VGs.

Observation of the anomalous current–voltage characteristics of GaAs/n+-InGaAs/GaAs doped-channel structure

A GaAs/n+-In0.2Ga0.8As/GaAs doped-channel field-effect transistor structure has been fabricated and studied. A typical transistor performance with a threshold voltage of about −3.0 V and transconductance of up to 160 mS/mm is obtained in the lower gate-source voltage (VGS <−1.0 V) regime. However, for some devices, the three-terminal-controlled N-shaped negative-differential-resistance (NDR) behavior is observed at the saturation regime of current–voltage characteristics under higher gate-source bias (VGS≥−1.0 V) condition. The interesting NDR phenomenon is believed to be attributed to the real-space transfer and deep-level electron trapping effect.

On the characterization of surface states and deep traps in GaAs MESFETs

A simple model of frequency-dependent transconductance ( g′ m( f)) is developed for characterizing surface states and bulk traps in GaAs metal semiconductor field effect transistors (MESFETs) by considering the occupancy modulation of the surface states and bulk traps. It is shown that the transconductance dispersion provides information for the determination of surface state and bulk trap energy levels. In particular, it is shown that the peak frequency in the transconductance spectrum, d g′ m( f)/d f vs f, is equal to the characteristic frequency of a surface state or a bulk trap that is responsible for the peak. Thus, the temperature dependence of the peak frequency facilitates the measurement of the surface state or bulk trap energy level. It is found that peaks due to surface states can be distinguished from those due to bulk traps in the gated channel region by their different dependence of peak heights on the gate-source reverse bias. A comparison of the theoretical results and the available experimental observations shows that the model can successfully explain both the surface leakage current dependence of transconductance dispersion magnitude reported by Ozeki et al. [ Inst. Phys. Conf. Ser., No. 63, pp. 323–328 (1982)] and the temperature dependence of transconductance dispersion observed by Blight et al. [ IEEE Trans. Electron Devices ED-35, 257–267 (1988)].

Frequency dependence of transconductance on deep traps in GaAs metal semiconductor field-effect transistors

A transconductance spectroscopy method is introduced through computer modeling which provides an easy way to the determination of energy levels of surface states and bulk traps in a GaAs metal semiconductor field-effect transistor. It is shown that in the transconductance spectrum each trap will result in a peak at a frequency which is equal to the characteristic frequency of the trap. It is suggested that peaks due to surface states can be distinguished from those due to bulk traps in the gated channel region by the dependence of the surface-state peak height on the gate-source reverse bias. It is found that previous experimental reports of transconductance dependence on temperature and surface leakage current can be explained by the model developed in this study.

Junction field-effect transistor single quantum well optical waveguide modulator employing the two-dimensional Moss–Burstein effect

A modulation-doped junction field-effect transistor incorporating an optical waveguide under the gate modulates light by the carrier band-filling effect (two-dimensional Moss–Burstein effect) in a single quantum well, achieving a 5:1 extinction ratio in a 250-μm-long waveguide for 4 V reverse gate-source bias Vgs swing and 0 V drain-source bias Vds. Similar performance is obtained over a 16 nm spectral range. A novel band-edge transparency effect is observed for Vds>0 allowing an extinction ratio of 10:1, corresponding to a change in absorption of 92 cm−1 to be obtained through band-gap dilation by hot electrons at biases of Vds =8 V. Below-band-gap refractive index modulation of 1.6×10−3 is obtained for a Vgs swing of 2.4 V. The novel junction field-effect transistor optical modulator also functions as a photovoltaic or photoconductive optical detector, a transistor, and a light-emitting diode.

Bias dependence of f/sub T/ and f/sub max/ in an In/sub 0.52/Al/sub 0.48/As/n/sup +/-In/sub 0.53/Ga/sub 0.47/As MISFET

Detailed microwave characterization of a recently fabricated In/sub 0.52/Al/sub 0.48/As/n/sup +/-In/sub 0.53/Ga/sub 0.47/As MISFET reveals that high values of current-gain cutoff frequency (f/sub T/) and unilateral-gain cutoff frequency (f/sub max/) are obtained for a broad range of gate bias voltage values. A significant peak in f/sub T/ and f/sub max/ has also been observed at high gate-source bias values. The peak coincides with the onset of electron accumulation at the heterointerface and is attributed to reduced ionized impurity scattering coupled with reduced drain conductance. This result suggests an improved device structure that optimizes operation in the accumulation regime. >

A semi-analytical approach to the evaluation of threshold voltage in depletion MOS's with nonuniformly doped substrates

D.A. Antoniadis' algorithm (ibid., vol.ED-31, no.3, p.303-7, 1984) is extended to cover the computation of threshold voltage for depletion or buried-channel MOSFETs. It is shown that a key factor in its evaluation, of the derivative of the integral charge of the mobile minority carriers in the substrate with respect to the gate-source bias, can easily be calculated using the concept of flat-band capacitance. The threshold voltage is thus computed without requiring strict numerical solution of Poisson's equation, yet the accuracy is very good. This modified algorithm has been implemented in SUPREM III, and good agreement between simulation and experimental results has been achieved. >