Gate-source Bias Research Articles

Solution‐Processed PTCDI‐C8 Crystalline Wire: Dual Role as Mask and Active Layer for Organic Transistors with Increased Switching Speeds

AbstractOrganic field‐effect transistors (OFETs) have been extensively studied over the past decades because of their suitability for low‐cost, large‐area, and flexible electronics. However, improvements are needed to satisfy the demands of high‐speed applications. The switching speed of a logic device is affected by the charge‐carrier mobility (µ) and the square of the channel length (L) at a given gate–source bias. Therefore, increasing µ and/or reducing L are crucial for achieving high‐speed OFET‐based digital circuits. In this study, an n‐type OFET is fabricated with increased switching speed via a dual‐role approach involving solution‐grown, highly ordered single‐crystalline N,N'‐dioctyl‐3,4,9,10‐perylenetetracarboxylic diimide (PTCDI‐C8) wires, which serve as a mask for short‐channel formation up to the microscale and an active layer with enhanced charge mobility. Additionally, the performance of the n‐type short‐channel OFET and resistive‐load‐type inverters is evaluated. For comparative purposes, long‐channel (50 µm) devices with PTCDI‐C8 wires and short‐channel devices with a PTCDI‐C8 film are fabricated and the device performance is analyzed. The short‐channel device with the PTCDI‐C8 wires exhibits a significantly higher switching speed. Thus, the dual‐role approach is a simple and straightforward method for fabricating short‐channel devices, paving the way for further advancements in OFET technology requiring high switching speeds.

Asynchronous Charge Carrier Injection in Perovskite Light‐Emitting Transistors

AbstractUnbalanced mobility and injection of charge carriers in metal‐halide perovskite light‐emitting devices pose severe limitations to the efficiency and response time of the electroluminescence. Modulation of gate bias in methylammonium lead iodide light‐emitting transistors has proven effective in increasing the brightness of light emission up to MHz frequencies. In this work, a new approach is developed to improve charge carrier injection and enhance electroluminescence of perovskite light‐emitting transistors by independent control of drain–source and gate–source bias voltages to compensate for space‐charge effects. Optimization of bias pulse synchronization induces a fourfold enhancement of the emission intensity. Interestingly, the optimal phase delay between biasing pulses depends on modulation frequency due to the capacitive nature of the devices, which is well captured by numerical simulations of an equivalent electrical circuit. These results provide new insights into the electroluminescence dynamics of AC‐driven perovskite light‐emitting transistors and demonstrate an effective strategy to optimize device performance through independent control of the amplitude, frequency, and phase of the biasing pulses.

Novel double channel reverse conducting GaN HEMT with an integrated MOS-channel diode

A novel normally-off double channel reverse conducting (DCRC) HEMT with an integrated MOS-channel diode (MCD) is proposed and investigated by TCAD simulation. The proposed structure has two features: one is double heterojunctions to form dual 2DEG channels named the 1st path and the 2nd path for reverse conduction, and the other is the MCD forming by the trench source metal, source dielectric, and GaN. At the initial reverse conduction stage, the MCD acts as a switch to control the 1st path which would be turned on prior to the 2nd path. Because of the introduction of the 1st path, the DCRC-HEMT has an additional reverse conducting channel to help enhance the reverse conduction performance. Compared with the conventional HEMT (Conv. HEMT), the DCRC-HEMT can obtain a low reverse turn-on voltage (V RT) and its V RT is independent of the gate–source bias (V GS) at the same time. The DCRC-HEMT achieves the V RT of 0.62 V, which is 59.7% and 75.9% lower than that of the Conv. HEMT at V GS = 0 V and −1 V, respectively. In addition, the forward conduction capability and blocking characteristics almost remain unchanged. In the end, the key fabrication flows of DCRC-HEMT are presented.

Modeling of a vertical tunneling transistor based on Gr-hBN- χ 3 borophene heterostructure

We present a computational study on the electrical behavior of the field-effect transistor based on vertical graphene-hBN-χ3 borophene heterostructure and vertical graphene nanoribbon-hBN-χ3 borophene nanoribbon heterostructure. We use nonequilibrium the Green function formalism along with an atomistic tight-binding (TB) model. The TB parameters are calculated by fitting tight-binding band structure and first-principle results. Also, electrical characteristics of the device, such as ION/IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. We show that the increase of the hBN layer number decreases subthreshold swing and degrades the intrinsic gate-delay time. The device allows current modulation 177 at room temperature for a 1.2 V gate-source bias voltage.

High temperature operation of a monolithic bidirectional diamond switch

We report the 250 °C operation of a diamond-based monolithic bidirectional switch. A normally-ON double gate deep depletion MOSFET was fabricated with a 400 nm p-type channel with a boron doping of [NA-ND] = 2.3 × 1017 cm−3 and an Al2O3 gate oxide thickness of 50 nm. The Ist and IIIrd quadrants transistor characteristics are successfully measured by controlling the channel conductivity with both gates separately, with a clear ON and OFF state. A threshold voltage around 35 V is obtained with a low minimum gate leakage current of 1.00 × 10−4 mA/mm at a gate-source bias VGS = 50 V. The bidirectional switch is then obtained by operating the MOSFET in the Ist quadrant of each gate setup. This first proof of concept offers a reverse conducting and reverse blocking diamond MOSFET, with only one drift region layer.

Investigation on Surge Current Capability of 4H-SiC Trench-Gate MOSFETs in Third Quadrant Under Various V GS Biases

In this work, third-quadrant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> characterization and surge current tests are carried out on SiC asymmetric-trench MOSFET (DUT A) and SiC double-trench MOSFET (DUT B) under various gate–source biases ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula> ). The surge capability is found to be uninfluenced by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula> for DUT A. However, it has a 71.4% increase when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula> changes from 0 to −5 V for DUT B. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> characteristics in the third quadrant are measured under various <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula> . It is found that the channel is open when the source–drain voltage is >2.5 V for DUT A and >1.5 V for DUT B at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V. High-temperature measurements are also conducted from 298 K to 448 K. When <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V, the channel current takes up to 50% at 10-A source-to-drain current for DUT B, whereas only 10% for DUT A. This could lead to high current/heat density in the channel of DUT B. The transient resistance is also extracted from the surge <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> trajectories, and it is higher for DUT B tested under <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V, which will increase the dissipated surge energy. Finally, the failure mechanism is analyzed. For DUT A, aluminum melting contributes to the failure at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}}= -5$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V. For DUT B tested at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {GS}} =0$ </tex-math></inline-formula> V, the earlier breakdown happens due to gate oxide failure.

Compact Model for L-Shaped Tunnel Field-Effect Transistor Including the 2D Region

The L-shaped tunneling field-effect transistor (LTFET) is the only line-tunneling type of TFET to be experimentally demonstrated. To date, there is no literature available on the compact model of LTFET. In this paper, a compact model of LTFET is presented. LTFET has both one-dimensional (1D) and 2D band-to-band tunneling (BTBT) components. The 2D BTBT part dominates in the subthreshold region, whereas the 1D BTBT dominates at higher gate-source biases. The model consists of 1D and 2D BTBT models. The 2D BTBT model is based on the assumption that the electric field originating from the gate and terminating at the source edge is perfectly circular. Tunneling path length is obtained by calculating the distance along an electric field arc that runs from gate to source. The 1D BTBT model is based on a simultaneous solution of the 1D Poisson equation in source and channel regions. Expressions for electric field and potential obtained from integrating the Poisson equation in source and channel regions are solved simultaneously to find the surface potential. Once the surface potential is known, all the other unknown variables, including junction potential and source depletion length, can be calculated. Using the potential profile, tunneling lengths were found for both the source-to-channel BTBT regime, and channel-to-channel BTBT regime. The tunneling lengths were used to calculate the BTBT tunneling rate, and finally, the drain-source current as a function of gate-source, and drain-source bias was calculated. The model results were compared against technology computer-aided design (TCAD) simulation results and were found to be in reasonable agreement for a compact model.

Trapped charge modulation at the MoS2/SiO2 interface by a lateral electric field in MoS2 field-effect transistors

Controlling trapped charges at the interface between a two-dimensional (2D) material and SiO2 is crucial for the stable electrical characteristics in field-effect transistors (FETs). Typically, gate-source bias has been used to modulate the charge trapping process with a narrow dielectric layer with a high gate electric field. Here, we observed that charge trapping can also be affected by the lateral drain-source voltage (VDS) in the FET structure, as well as by the gate-source bias. Through multiple VDS sweeps with increasing measurement ranges of the VDS, we demonstrated that the charge trapping process could be modulated by the range of the applied lateral electric field. Moreover, we inserted a hexagonal boron nitride (h-BN) layer between the MoS2 and SiO2 layer to explore the charge trapping behavior when a better interface is formed. This study provides a deeper understanding of controlling the electrical characteristics with interface-trapped carriers and lateral electrical fields in 2D material-based transistors.

Breakdown mechanism in 1 kA/cm2 and 960 V E-mode β-Ga2O3 vertical transistors

A high current density of 1 kA/cm2 is experimentally realized in enhancement-mode Ga2O3 vertical power metal-insulator field-effect transistors with fin-shaped channels. Comparative analysis shows that the more than doubled current density over the prior art arises from a larger transistor channel width; on the other hand, a wider channel also leads to a more severe drain-induced barrier lowering therefore premature transistor breakdown at zero gate-source bias. The observation of a higher current density in a wider channel confirms that charge trapping in the gate dielectric limits the effective field-effect mobility in these transistor channels, which is about 2× smaller than the electron mobility in the Ga2O3 drift layer. The tradeoff between output-current density and breakdown voltage also depends on the trap density. With minimal trap states, the output current density should remain high while breakdown voltage increases with decreasing fin-channel width.

Modeling the Reverse Gate-Leakage Current in GaN-Channel HFETs: Realistic Assessment of Fowler–Nordheim and Leakage at Mesa Sidewalls

A model considering different leakage paths for describing the reverse gate leakage in mesa-isolated polar GaN-channel heterostructure field-effect transistors (HFETs) is presented. For AlGaN/GaN HFETs, it is illustrated that for small negative values of gate–source bias, gate leakage happens from the gate-covered mesa sidewalls to the 2-D electron gas (2-DEG). The bias and temperature dependences of the gate current show that the sidewall path to the 2-DEG is associated with the Poole–Frenkel electron emission. As the gate–source bias becomes more negative, electrons choose a different path to the 2-DEG. In this case, results corroborate that the gate leakage is dominated by the Fowler–Nordheim (FN) direct tunneling process through the III-nitride barrier. The novel contribution of the present analysis is that it postulates that in absence of absolute uniformity, FN tunneling takes place through only a small portion of the surface of the barrier, which boasts the highest electric field or the smallest Schottky barrier height. By applying this hypothesis, the origin of the inconsistencies inherent to the previously presented models in selecting the value of the electron effective mass can be explained.

Utilizing Schottky barriers to suppress short-channel effects in organic transistors

Transistors with short channel lengths exhibit profound deviations from the ideally expected behavior. One of the undesired short-channel effects is an enlarged OFF current that is associated with a premature turn on of the transistor. We present an efficient approach to suppress the OFF current, defined as the current at zero gate source bias, in short-channel organic transistors. We employ two-dimensional device simulations based on the drift-diffusion model to demonstrate that intentionally incorporating a Schottky barrier for injection enhances the ON-OFF ratio in both staggered and coplanar transistor architectures. The Schottky barrier is identified to directly counteract the origin of enlarged OFF currents: Short channels promote a drain-induced barrier lowering. The latter permits unhindered injection of charges even at reverse gate-source bias. An additional Schottky barrier hampers injection for such points of operations. We explain how it is possible to find the Schottky barrier of the smallest height necessary to exactly compensate for the premature turn on. This approach offers a substantial enhancement of the ON-OFF ratio. We show that this roots in the fact that such optimal barrier heights offer an excellent compromise between an OFF current diminished by orders of magnitude and an only slightly reduced ON current.

Characterization of Parasitic Resistances of AlN/GaN/AlGaN HEMTs Through TCAD-Based Device Simulations and On-Wafer Measurements

This paper shows a detailed characterization and estimation of the temperature-dependent on-resistance $R _{\mathrm {ON}}~( T )$ of AlN/GaN/AlGaN high electron-mobility transistors (HEMTs) through dc and low-frequency (LF) S-parameter measurements. The measurements are carried out at different chuck temperatures $( T _{\mathrm {chuck}} )$ and the $R _{\mathrm {ON}}~( T )$ is calculated for different values of gate-source bias $( V _{\mathrm {GS}} )$ of HEMT grown on a silicon carbide (SiC) substrate. Furthermore, we also present the two-dimensional (2-D) physics-based numerical simulation results for the $R _{\mathrm {ON}}~( T )$ extraction of this device. Knowing $R _{\mathrm {ON}}~( T )$ values of the device for different source-drain lengths $( L _{\mathrm {SD}} )$ , we propose a simplified method to extract the temperature-dependent series contact resistance $R _{\mathrm {se}}~( T )$ and channel sheet resistance $R _{\mathrm {sh}}~( T )$ of the GaN HEMT technology.

Photoelectronic Effects with Graphene Channels Interfaced with Quantum Dots Arrays

The electrical and photo-electronic properties of graphene-based field effect transistors (GFETs) were studied when the single layer graphene served as the transistor channel, while interfaced with well organized, isolated semiconductor quantum dots (QD) array. The photoluminescence (PL) of the QDs as a function of the drain-source (Vds) and the gate-source (Vgs) bias was studied. Graphene, a two-dimensional, single layer thick crystalline form of carbon atoms, has outstanding physical properties, such as high conductivity, chemical inertness, mechanical robustness and unusual dispersion relations [1]. In the past, we studied graphene layer(s) when suspended over nano-pore structures [2-6]. Here we used anodized aluminum oxide (AAO) as the perforated substrate, and core/shell CdSe/ZnS semiconductor quantum dots (QD) as the photo-sensitive material. The QD were imbedded in the AAO pores. The GFETs were fabricated by transferring a single layer of graphene on top of the QD imbedded AAO. The array of holes on the AAO substrate were 25-30 nm in diameter and with a pitch of 100 nm. For the photoluminescence (PL) measurements, a 10 mW Ar ion laser at 488 nm was used in confocal arrangement. Coupling of the incident and/or emitted light with the surface Plasmon/Polariton (SPP) mode was observed as a peak in PL curve as a function of the sample's tilt angle with respect to the incident optical beam. The fluorescence peak of the QDs decreased monotonously as a function of Vgs and Vds alluding to the control of PL by the biasing potentials. The effect of white-light intensity on the sample conductivity was studied, as well: the difference in Ids between illuminated and non-illuminated cases was substantially affected by the biasing potentials. [1] K.S. Novoselov, A.K. Geim, S.V. Morozov, D. Jiang, Y. Zhang, S.V. Dubonos, I.V. Grigorieva and A.A. Firsov, “ Electric Field Effect in Atomically Thin Carbon Films”, Science, 306, 666 (2004). [2] A. Banerjee, R. Li and H. Grebel, “Surface Enhanced Raman with Graphenated Anodized Aluminum Oxide Substrates: the Effect of Sub-Wavelength Patterns”, Nanotechnology, 20 (29), art. no. 295502 (2009). [3] A. Banerjee and H. Grebel, “Depositing Graphene Films on Solid and Perforated Substrates”, Nanotechnology, 19 1-5 art. no. 365303 (2008). [4] Ruiqiong Li, and Grebel Haim, “Surface Enhanced Fluorescence”, IEEE Sensors, 10(3), 465-468 (2010) doi: 10.1109/JSEN.2009.2038513. [5] R. Li, A. Banerjee and H. Grebel, “The possibility for surface plasmon lasers”, Optics Express, 17, 1622-1627 (2009). [6] A. Banerjee, R. Li and H. Grebel, "Surface plasmon lasers with quantum dots as gain media", Appl. Phys. Letts., 95, 251106 (2009); doi:10.1063/1.3276273.

A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating

In this work, a methodology based on the E-model for the reliability projection of a thick (>20nm) SiO2 gate oxide on a vertical trench power MOSFET, is presented. Experimental results suggest that a Logic Level (LL) trench MOSFET with 35nm of gate oxide can be rated at VGS=+12V if one assumes continuous DC Gate-Source bias of VGS=+12V at T=175°C for 10years at a defect level of 1 Part Per Million (PPM). We will demonstrate that if we take into account MOSFET device lifetime as dictated by the Automotive Electronics Council (AEC Q101) mission profile, then devices can be rated higher to VGS=+14.7V at T=175°C for the same PPM level (1PPM). The application of the methodology for establishing the oxide thickness, tox, for any required voltage rating, is discussed.

Wideband complementary metal–oxide–semiconductor double‐bulk harmonic‐rejection mixer

This paper presents the design and testing results of a complementary metal–oxide–semiconductor double-bulk harmonic-rejection (HR) mixer for wideband applications. An optimal gate-source bias voltage in the sub-threshold regime of the input transistor is found theoretically to achieve maxim HR by analysing the mixing mechanism of double-bulk mixer; and a double-bulk mixer has been designed and fabricated to verify the theoretical analysis. Test results substantiate the existence of the optimal bias point for HR of double-bulk-driven mixer when the sinusoidal local oscillator (LO) is applied. This simple but effective topology can achieve higher than 36, 44, 60 and 62 dB HR ratio for the third-, fifth-, seventh- and ninth-order of LOs, respectively, over broadband. The double-bulk mixer which input bandwidth is from 250 MHz to 3 GHz, including the buffer, consumes 5 mA current from 1 V power supply; the mixer core only consumes 1.5 mA current.

Universal analytic model for tunnel FET circuit simulation

A simple analytic model based on the Kane–Sze formula is used to describe the current–voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model also captures the ambipolar current characteristic at negative gate–source bias and the negative differential resistance for negative drain–source biases. A simple empirical capacitance model is also included to enable circuit simulation. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junction.

Electrical and Photo-Induced Effects in Graphene Channels When Interfaced with Quantum Dots

ABSTRACTField effect transistors with graphene channels were interfaced with arrays of semiconductor quantum dots (QD). The electrical characteristics of the elements were assessed. The channel response to white light illumination was also assessed as a function of drain-source and gate-source biases.

Density of states of amorphous In-Ga-Zn-O from electrical and optical characterization

We have developed a subgap density of states (DOS) model of amorphous In-Ga-Zn-O (a-IGZO) based on optical and electrical measurements. We study the optical absorption spectrum of the a-IGZO using UV-Vis spectroscopy. Together with the first-principles calculations and transient photoconductance spectroscopy from the literature, we determine that the valence band tail and deep-gap states are donors and can be described by exponential and Gaussian distributions, respectively. The conduction band tail and deep-gap states are examined using multi-frequency capacitance-voltage spectroscopy on a-IGZO thin-film transistors (TFTs). The extracted conduction band DOS are fitted to exponential (bandtail) and Gaussian (deep-gap) functions and their validity are supported by the activation energy vs. gate-source bias relationship of the a-IGZO TFT. The PL deep-level emission, which is almost identical to the conduction band deep-gap Gaussian, suggests that these states should be assigned as acceptors. The donor/acceptor assignments of subgap states are consistent with the 2D numerical TFT simulations.

Influence of polarization coulomb field scattering on the subthreshold swing in depletion-mode AlGaN/AlN/GaN heterostructure field-effect transistors

Using the measured capacitance–voltage (C–V) curves and current–voltage (I–V) curves for the prepared AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs), the relationship between polarization Coulomb field scattering (PCF scattering) and the subthreshold swing for depletion mode (D-mode) AlGaN/AlN/GaN HFETs has been investigated. It was found that the S value (S=(∂lg(IDS)/∂VGS)−1) of subthreshold swing is smaller for the device with the stronger PCF scattering, and the S value decreases by more than 26% for the D-mode AlGaN/AlN/GaN HFET samples. The reason is attributed to the big gradient of the mobility and the gate-source bias curve which is generated by the PCF scattering.

Transport properties of SiO2/AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors on SiC substrate

Unpassivated SiO2/AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs) exhibiting a thin barrier layer are investigated with a particular focus on their dc characteristics dependence on the gate length. The epiwafer exhibits a sheet resistance of ∼250 Ω/□ and a channel charge density of 7.4 × 1012 cm−2 deduced from the 1 MHz capacitance–voltage curves. The results indicate that the thickness of the AlInN barrier can be reduced below 5 nm without degradation of the insulated gate devices performance. For transistors with gate lengths (LG) between 1.8 and 2.0 µm, dc drain saturation currents densities as high as 1.8 A mm−1 are achieved at +4 V gate–source bias (VGS) with very low reverse gate leakage currents. The electron zero-bias drift mobility was determined to be 1670 cm2 V−1 s−1 from the low-field channel conductance measurements. On the other side, using an analytical model it is found that the maximum output current density at VGS = 0 V can be enhanced by ∼23% when LG is scaled from 1.8 µm down to 100 nm. With further improvement of the quality of the gate insulating oxide layer and the implementation of surface passivation, both with the aim of suppressing the observed current collapse, the presented results suggest that these MOSHEMTs could become very attractive for the realization of high-power electronics.