Abstract
The L-shaped tunneling field-effect transistor (LTFET) is the only line-tunneling type of TFET to be experimentally demonstrated. To date, there is no literature available on the compact model of LTFET. In this paper, a compact model of LTFET is presented. LTFET has both one-dimensional (1D) and 2D band-to-band tunneling (BTBT) components. The 2D BTBT part dominates in the subthreshold region, whereas the 1D BTBT dominates at higher gate-source biases. The model consists of 1D and 2D BTBT models. The 2D BTBT model is based on the assumption that the electric field originating from the gate and terminating at the source edge is perfectly circular. Tunneling path length is obtained by calculating the distance along an electric field arc that runs from gate to source. The 1D BTBT model is based on a simultaneous solution of the 1D Poisson equation in source and channel regions. Expressions for electric field and potential obtained from integrating the Poisson equation in source and channel regions are solved simultaneously to find the surface potential. Once the surface potential is known, all the other unknown variables, including junction potential and source depletion length, can be calculated. Using the potential profile, tunneling lengths were found for both the source-to-channel BTBT regime, and channel-to-channel BTBT regime. The tunneling lengths were used to calculate the BTBT tunneling rate, and finally, the drain-source current as a function of gate-source, and drain-source bias was calculated. The model results were compared against technology computer-aided design (TCAD) simulation results and were found to be in reasonable agreement for a compact model.
Highlights
With the power requirements of complementary metal–oxide–semiconductor (CMOS) technology surging beyond unreasonable levels to meet the high computing demands of today’s world, there has been a desperate push for devices that can perform better for less power [1]
The 1D model is based on the simultaneous solution of 1D Poisson equations in the channel and source region
The Poisson equation is integrated twice in both regions, and the expression for electric field and potential are equated at the source–channel junction point to yield expression for surface potential
Summary
With the power requirements of complementary metal–oxide–semiconductor (CMOS) technology surging beyond unreasonable levels to meet the high computing demands of today’s world, there has been a desperate push for devices that can perform better for less power [1]. Than a metal–oxide–semiconductor field-effect transistor (MOSFET) of equivalent dimensions and electrical parameters. The on-current (ION ) of TFET is lower than that of MOSFET of equivalent dimensions/electrical parameters. To overcome this problem, different types of TFET architectures have been suggested, including the line-tunneling type [3] TFETs. The structure of line tunneling type. LTFET, channel present between source the andsource the gate. Direct overlapping of gate/source channel any layer presentlayer in between changes thechanges electrostatics of the device anddevice makesand the without channel present completely in between completely the electrostatics of the model the presented [3] inapplicable to LTFET. LTFETs with with varying varying geometries, geometries, and and the the results results are are presented presented in in inversion
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