Gate Sizing Research Articles

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions

Modern systems-on-a-chip and microprocessors, e.g., those in smart phones and laptops, typically have multiple operating conditions, such as video streaming, Web browsing, standby, and so on. They will have different performance targets and run under different supply voltages. Gate sizing (with threshold voltage assignment) is a fundamental step for power/performance optimization. However, conventional gate sizing algorithms only consider one scenario, e.g., the performance-critical operating condition, which may be over-design for other operating conditions. In addition, reliability has become a prime concern in nanometer designs, and gate sizing has been employed to mitigate aging. However: 1) previous aging-affected delay models do not take into account more than one operating condition to estimate the aging impact and 2) earlier aging aware gate sizing algorithms only consider one operating condition at a time. In this paper, we present a new paradigm of aging aware gate sizing, one-size-fits-all (OSFA), which performs power/performance optimizations across multiple operating conditions. The existing delay model for negative bias temperature instability (NBTI) is extended to take into account multiple operating conditions, and incorporated into our OSFA framework. Based on OSFA, we also adjust the supply voltage targeting overall power optimization. A speed-up heuristic is proposed to scale our OSFA design space exploration methodology for higher number of operating conditions. Experimental results on industry-strength benchmarks demonstrate that: 1) compared with conventional approach OSFA could provide an average 6.1% reduction in power without performance loss; 2) NBTI-aware OSFA framework can provide significant improvement in comparison with guard-band based traditional NBTI-aware gate sizing approach; and 3) percentage savings compared to conventional methodology increases with the number of operating conditions.

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient

In this article, we derive a simple and accurate expression for the change in timing yield due to a change in the gate delay distribution. It is based on analytical bounds that we have derived for the moments of the circuit and path delay. Based on this, we propose computationally efficient algorithms for (1) discrete gate sizing and (2) simultaneous gate sizing and threshold voltage ( V T ) assignment so that the circuit meets a timing yield specification under parameter variations. The use of this analytical yield gradient within a gradient-based timing yield optimization algorithm results in a significant improvement in the runtime as compared to the numerical method, while achieving the same final yield. It also allows us to explore a larger search space in each iteration more efficiently, which is required in the case of simultaneous resizing and V T assignment. We also propose heuristics for resizing/changing the V T of multiple gates in each iteration. This makes it possible to optimize the timing yield for large circuits. Results on ITC ’99 benchmarks show that the proposed multinode resizing algorithm results in a significant improvement in the runtime with a marginal average area penalty and no cost to the final yield achieved.

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization

A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to maximize NTV mode clock frequency. Some cells that are particularly slow in NTV mode are optimized through transistor sizing and stack removal; static noise margin of each gate is extracted and appended in a library so that function failures can be checked and removed during synthesis. A new gate-sizing algorithm is proposed that takes account of timing slacks at both modes. A new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV mode frequency. Clock-tree synthesis is reformulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock-path delays themselves, should be made equal. Experiments on some test circuits indicate that NTV mode clock period is reduced by 24%, on average; clock skew at NTV decreases by 13%, on average; and NTV mode energy-delay product is reduced by 20%, on average.

Clock Period Minimization with Minimum Leakage Power

In the design of nonzero clock skew circuits, an increase of the short-path delay may improve circuit speed or reduce leakage power. However, the impact of increasing the short-path delay on the trade-off between circuit speed and leakage power has not been well studied. An analysis of previous works shows that they can be classified into two independent groups. One group uses extra buffers to increase the short-path delay for achieving the lower bound of the clock period; however, this group has a large overhead of leakage power. The other group uses the combination of threshold voltage assignment and gate sizing (TVA/GS) to increase the short-path delay as possible for reducing leakage power; however, this group often does not work with the lower bound of the clock period. Accordingly, this article considers the simultaneous application of buffer insertion and TVA/GS during clock skew scheduling. Our objective is to minimize the leakage power for working with the lower bound of the clock period. To the best of our knowledge, our approach is the first leakage-power-aware clock skew scheduling that guarantees working with the lower bound of the clock period. Benchmark data consistently show that our approach achieves good results in terms of both the circuit speed and the leakage power.

Technology-Dependent Logic Optimization

In modern design flows, technology-dependent logic optimizations consist of technology mapping and transformations applied after mapping. Advances have been made in technology mapping in the last decade. However, it is inherently an intractable problem and state-of-the-art algorithms produce suboptimal netlists in terms of area and timing. Also, during the design flow, when physical information becomes available, wire loads and net delays change the timing values at the gates. That presents opportunities for further timing and area optimization. This is accomplished by transforms such as gate sizing, gate replication, buffer optimization, restructuring and remapping, and pin permutation. In this paper, we survey algorithms for technology-dependent optimizations, along with a comparison of their relative power to optimize the netlist.

Challenges of cell selection algorithms in industrial high performance microprocessor designs

Timing-constrained power-driven gate sizing has aroused lot of research interest after the recent discrete gate sizing contests organized by International Symposium on Physical Design. Since then, there are plenty of research papers published and new algorithms are proposed based on the contest formulation. However, almost all (new and old) papers in the literature ignore the details of how power-driven gate sizing fits in industrial physical synthesis flows, which limits their practical usage. This paper aims at filling this knowledge gap. We explain our approach to integrate a state-of-the-art Lagrangian Relaxation-based gate sizing into our actual physical synthesis framework, and explain the challenges and issues we observed from the point of view of VLSI design flows.

A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs

Soft errors have been a critical concern for reliability of advanced CMOS designs due to technology scaling. Moreover, along with the rapid growth of medical, automotive, and aerospace electronics, extremely high demand on reliability becomes the paramount concern, superior to cost and performance, on these safety-critical designs. Triple modular redundancy (TMR) is widely used to mask virtually all soft errors but typically incurs high power and area overheads. Therefore, in this paper, a determinate radiation hardened technique for safety-critical CMOS designs is proposed and consists of three hybrid strategies combining gate sizing, supply voltage (V D D ) scaling and threshold voltage (V t h ) scaling to prevent soft errors from occurring. A STA-like method that computes the required pulse width of a transient fault along the propagation path is also developed in this framework. Simulation results show that the proposed technique can effectively eliminate all soft errors on ISCAS'85 circuits and a controller area network bus electrical control unit (CAN-bus ECU) design for automotive electronics when the deposited charges range from 35 fC to 132 fC. Furthermore, the strategy using all three techniques, simultaneously improves power and area overheads by 3.3X and 2X, respectively, compared with TMR.

An Evolutionary Approach to the Soft Error Mitigation Technique for Cell-Based Design

In this paper, we present a soft error mitigation algorithm that searches for the proper gate sizes within constrained gate-level designs. The individual gate sizing has an impact on t ...

NBTI tolerance and leakage reduction using gate sizing

Leakage power is a major design constraint in deep submicron technology and below. Meanwhile, transistor degradation due to Negative Bias Temperature Instability (NBTI) has emerged as one of the main reliability concerns in nanoscale technology. Gate sizing is a widely used technique to reduce circuit leakage, and this approach has recently attracted much attention with regard to improving circuits to tolerate NBTI. However, these studies only consider timing and area constraints, and many other important issues, such as slew and max-load, are missing. In this article, we present an efficient gate sizing framework that can reduce leakage and improve circuit reliability under timing constraints. Our algorithms consider slack, slew and max-load constraints. The benchmarks are those from ISPD 2012, which feature industrial design properties, including discrete cell sizes, nonconvex cell timing models, slew dependencies and constraints, as well as large design sizes. The experimental results obtained from ISPD 2012 benchmark circuits demonstrate that our approach can meet all the constraints and tolerated NBTI degradation with a power savings of 6.54% as compared with the traditional method.

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discrete nature of the problem, along with complex timing models, stringent design constraints, and ever-increasing circuit sizes, make the problem very difficult to tackle. Lagrangian Relaxation (LR) is an effective technique to handle complex constrained optimization problems and therefore has been successfully applied to solve the gate sizing problem. This article proposes an improved Lagrangian relaxation formulation for discrete gate sizing that relaxes timing, maximum gate input slew, and maximum gate output capacitance constraints. Based on such formulation, we propose a hybrid technique composed of three steps. First, a topological greedy heuristic solves the LR formulation. Such a heuristic is applied assuming a slightly increased target clock period (backoff factor) to better explore the solution space. Second, a delay recovery heuristic reestablishes the original target clock with small power overhead. Third, a power recovery heuristic explores the remaining slacks to further reduce power. Experiments on the ISPD 2012 Contest benchmarks show that our hybrid technique provides less leakage power than the state-of-the-art work for every circuit from the ISPD 2012 Contest infrastructure, achieving up to 24% less leakage. In addition, our technique achieves a much better compromise between leakage reduction and runtime, obtaining, on average, 9% less leakage power while running 8.8 times faster.

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation

This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than and 12.45% smaller than . The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest.

Robust Optimization for Gate Sizing Considering Non-Gaussian Local Variations

This paper employs a new second-order cone (SOC) model as the uncertainty set to capture non-Gaussian local variations. Then using robust gate sizing as an example, we describe the detailed procedures of robust design with a budget of uncertainty. For a pre-selected probability level of yield protection, this robust method translates uncertainty budgeting problems into regular robust optimization problems. More importantly, under the assumption of non-Gaussian distributions, we show that within-die variations will lead to varying sizes of uncertainty sets at different nominal values. By using this new model of uncertainty estimation, the robust gate sizing problem can be formulated as a Geometric Program (GP) and therefore efficiently solved.

Optimal gate sizing using a self-tuning multi-objective framework

In this paper, we present a self-tuning multi-objective framework for geometric programming that provides a fine trade-off between the competing objectives. The significance of this framework is that the designer does not need to perform any tuning of weights of objectives. The proposed framework is applied to gate sizing and clock network buffer sizing problems. In gate sizing application, power consumption is reduced on average by 86% while delay sees only an increase of 34ns. In clock network butter sizing application, our framework results in a significant reduction in power, 57%, and an improvement of 31ps in skew.

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution-based analysis. The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.

ECO cost measurement and incremental gate sizing for late process changes

Changes in the manufacturing process parameters may create timing violations in a design, making it necessary to perform an engineering change order (ECO) to correct these problems. We present a framework for performing incremental gate sizing for process changes late in the design cycle, and a method for creating initial designs that are robust to late process changes. This includes a method for measuring and estimating ECO cost and for transforming these costs into linear programming optimization problems. In the case of ECOs, the method reduces ECO costs on average, by 89% in changed area compared to a leading commercial tool. Furthermore, the robust initial designs are, on average, 55% less likely to need redesign in the future.

TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders

Due to increasing integrated circuit design complexity, engineering change orders (ECOs) have become a necessary technique to resolve late-found functional errors and/or performance deficiencies. To fix timing violations, gate sizing and buffer insertion are commonly used in postmask ECO. These techniques, however, may not be powerful enough, especially when spare cells are inserted to balance between functional and timing repair capabilities. We propose a postmask ECO technique, called TRECO, to remedy timing violations based on technology remapping, which also supports functional ECO. Unlike conventional technology mapping, TRECO performs technology mapping with respect to a limited set of spare cells and confronts dynamic changes of wiring cost incurred by selection of different spare cells. With a precomputed lookup table of representative circuit templates, TRECO iteratively performs technology remapping to restructure timing critical subcircuits until no timing violation can be further removed. Experimental results on five industrial designs show the effectiveness of TRECO in ECO timing optimization and in timing-aware functional ECO.

Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs

It is becoming increasingly important to design high-performance circuits with as low power as possible. In this paper, we study the gate sizing and device parameter selection problem for today's industrial designs. We first outline the typical practical problems that make it difficult to use traditional algorithms on high-performance industrial designs. Then, we propose a Lagrangian relaxation-based formulation that decouples timing analysis from optimization without a resulting loss in accuracy. We also propose a graph model that accurately captures discrete cell-type characteristics based on library data. We model the relaxed Lagrangian subproblem as a graph problem and propose algorithms to solve it. In our experiments, we demonstrate the importance of using the signoff timing engine to guide the optimization. We also show the benefit of the graph model we propose to solve the discrete optimization problem. Compared to a state-of-the art industrial optimization flow, we show that our algorithms can obtain up to 38% leakage power reductions and better overall timing for real high-performance microprocessor blocks.

Gate sizing using geometric programming

A two-step transistor sizing optimization method based on geometric programming for delay/area minimization is presented. In the first step, Elmore delay is minimized using only minimum and maximum transistor size constraints. In the second step, the minimized delay found in the previous step is used as a constraint for area minimization. In this way, our method can target simultaneously both delay and area reduction. Moreover, by relaxing the minimized delay, one may further reduce area with small delay penalty. Gate sizing may be accomplished through transistor sizing tying each transistor inside a cell to a same scale factor. This reduces the solution space, but also improves runtime as less variables are necessary. To analyze this tradeoff between execution time and solution quality a comparison between gate sizing and transistor sizing is presented. In order to qualify our approach, the ISCAS’85 benchmark circuits are mapped to a 45 nm technology using a typical standard cell library. Gate sizing and transistor sizing are performed considering delay minimization. Gate sizing is able to reduce delay in 21 %, on average, for the same area and power values of the sizing provided by standard-cells library. Then, the transistor sizing is executed and delay can be reduced in 40.4 % and power consumption in 2.9 %, on average, compared to gate sizing. However, the transistor sizing takes about 23 times longer to be computed, on average, using a number of variables twice higher than gate sizing. Gate sizing optimizing area is executed considering a delay constraint. Three delay constraints are considered, the minimum delay given by delay optimization and delay 1 and 5 % higher than minimum delay. An energy/delay gain (EDG) metric is used to quantify the most efficient tradeoff. Considering the minimum delay, area (power) is reduced in 28.2 %, on average. Relaxing delay by just 1 %, area (power) is reduced in 41.7 % and the EDG metric is 41.7. Area can be reduced in 51 %, on average, relaxing delay by 5 % and EDG metric is 10.2.

A gate sizing and transistor fingering strategy for subthreshold CMOS circuits

Parallel Transistor Stacks (PTS) has been shown to be an effective technique for improving the speed of digital circuits operating in the subthreshold region which comes at the cost of power consumption and area. However, our experience shows that using PTS is not beneficial in all cases. In this paper, we present a methodology to identify whether using PTS is beneficial (or not) in a particular CMOS technology and what transistor sizing can be employed to maximize the circuit speed. Our technique is based on analyzing the Current-Over-Capacitance (COC) ratio of PMOS and NMOS transistors. The results of incorporating the proposed methodology in a 4-bit comparator and a 19-stage inverter ring oscillator, using 90nm CMOS technology, illustrate 26% and 40% extra improvement compared to the blind use of PTS, respectively.