Gate Sizing Research Articles

Optimizing integrated circuits: Design and analysis of an efficient 4-bit absolute-value detector

Amidst rapid advancements in the realm of computer science, integrated circuits emerge as pivotal to technological progression, influencing a diverse range of sectors significantly. This study delves into a 4-bit absolute-value detector, a crucial tool in signal detection, which evaluates the magnitude of a given inputs absolute value against a predetermined threshold and conveys the outcome. The paper presents an innovative, optimized design for a 4-bit absolute-value detector, employing CMOS technology. A novel, efficient 3-bit adder is developed and incorporated in the circuit to minimize gate delay and energy usage. By fine-tuning the applied voltage (Vdd) and implementing gate sizing, the delay is maintained at approximately 1.5 times the minimum possible delay, while ensuring low power consumption. The defined parameters for this detector are 145.05 FO4 (0.82V) and 7.23C Eu (0.82V). The design methodologies and strategic insights shared in this paper form a foundational basis for future enhancements in signal processing technologies, potentially driving these fields towards a path of accelerated, robust, and sustainable growth.

AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL

Gate sizing and buffer insertion for timing optimization are performed extensively in electronic design automation (EDA) flows. Both of them aim to adjust the upstream and downstream capacitances of gates/buffers to minimize delay. However, most of existing work focuses on gate sizing or buffer insertion independently. This paper proposes a learning-based timing optimization framework, AiTO, that combines reinforcement learning with graph neural network, to perform simultaneously gate sizing and buffer insertion. We model buffer insertion as a special gate sizing by determining possible buffer locations in advance and treating the buffer insertion and gate sizing as an RL process. Experimental results on 10 real designs (28-nm and 110-nm) show that, AiTO can achieve better worst negative slack (WNS) optimization results than OpenROAD while being able to improve the results of the commercial tool, Innovus, to some extent. Moreover, ablation studies demonstrate the benefits of performing simultaneous gate sizing and buffer insertion for timing optimization.

A methodology of designing and optimising a 4-bit absolute-value detector for the application of Brain-computer Interface

Digital integrated circuits perform logical operations through several modules composed of logic gates. As a common module in digital circuits, the absolute value detector is applied to compare the absolute value of two binary inputs and can be further used for data sorting and searching. In clinical medicine, the detector can receive biological data from the sensor and control the instrument on the operating table. A typical application is Brain-computer Interface (BCI). Therefore, the performance of detectors is significant to electronic devices like computers. The optimisation of detectors usually concentrates on their propagation delay and power consumption. But theoretical optimisation will inevitably use simple logic and have large fan-in, and it is difficult to be implemented in practice. Here we explore an alternative plan that is more convenient to be produced in the industry, which combines static complementary metal-oxide semiconductor (CMOS) technology and transmission gates. After gate sizing, the critical path calculates the propagation delay and energy based on the logical effort theory. Finally, the relationship between energy and delay is analysed by scaling the voltage supply and the minimum energy occurs when the delay grows to 1.5 times the minimum delay.

A New Design of A 6-Bit Absolute Value Detector by Using Both VDD Scaling and Sizing to Optimize

The presented paper focuses on the development and optimization of a 6-bit absolute value detector, a crucial digital block in encoder and decoder applications. The primary objective is to minimize energy consumption while maintaining a delay no greater than 1.5 times the minimum delay. The optimization process combines logical effort theory with gate sizing and voltage scaling techniques. Firstly, gate sizes are adjusted while keeping VDD constant, achieving a 73% reduction in energy consumption, reaching a delay constraint of 1.5 times the minimum delay. Secondly, VDD scaling is explored without altering gate sizes, resulting in a 40% reduction in energy consumption, reaching the minimum energy consumption point. Finally, gate sizing and VDD scaling are combined, yielding a remarkable 79% reduction in total energy consumption, with a supply voltage of 0.835 volts. These optimization strategies bridge a research gap in 6-bit absolute value detectors, significantly enhancing energy efficiency and offering valuable insights for intricate digital signal processing scenarios. The findings showcase the effectiveness of combining logical effort theory with gate sizing and voltage scaling to achieve substantial energy savings while meeting stringent delay constraints.

Learning-driven Physically-aware Large-scale Circuit Gate Sizing

Learning-driven Physically-aware Large-scale Circuit Gate Sizing

Enhancing Surface Electromyography (sEMG) Signal Processing through a Four-bit Absolute Value Comparator

This paper delves into the realm of Surface Electromyography (sEMG) signal processing, presenting a comprehensive exploration of its theoretical underpinnings and the application of a four-bit absolute value comparator. The journey commences with an introduction to the subject matter, followed by an in-depth analysis of the theoretical basis of sEMG signals, encompassing their definition and waveform characteristics, as well as the processing flow. The focal point of this study is the utilization of a four-bit absolute value comparator in enhancing sEMG signal processing. Moving forward, the paper delves into the intricacies of logic circuit design, elucidating the architecture of both adder and comparator circuits pivotal in this context. Circuit optimization strategies are subsequently unveiled, addressing critical path considerations, gate sizing, and VDD optimization to bolster efficiency. In summation, this research advances our understanding of sEMG signal processing and introduces a novel four-bit absolute value comparator, which holds promise in elevating the precision and reliability of sEMG data analysis.

Analysis Of 4-Bit Absolute Value Detector for ECG Signal Comparation

In the present era, where numerous heart conditions are prevalent, the significance of monitoring cardiac electrical signals has surged within the medical realm. Within this study, we leverage Complementary Metal Oxide Semiconductor (CMOS) and Pass-transistor Logic (PTL) methodologies for crafting and refining a 4-bit absolute value detection mechanism. This mechanism serves to identify and juxtapose electrocardiogram (ECG) signals. The 4-bit absolute value detection system is bifurcated into two core segments: one for absolute value identification and the other for comparative analysis. This setup facilitates a binary input's comparison with a predetermined threshold, thereby yielding a corresponding comparative outcome. Subsequently, a meticulous assessment is conducted on the lengthiest pathway, which is then subject to refinement through gate sizing and voltage supply (Vdd) adjustments. The findings unveil a delay of 34.13tp0 and an energy dissipation of 184.832 C. The resultant 4-bit absolute value detection mechanism, borne from this research institution's efforts, emerges as an invaluable asset in the medical domain, attributed to its exceptional optimization with respect to minimal delay and energy outlay.

An Improved Design of Absolute-value Detector by Using Optimized Ripple Adder

Absolute-value detector (AVD) is one of the most basic bit-operating devices, which compares the magnitude of two inputs. However, the traditional 4-bit AVD is not only time-consuming but also has a high energy consumption. This paper uses a hybrid design to optimize the 4-bit AVD by introducing an improved ripple adder in the absolute value extraction part, which then can be less energy-consuming and requires fewer transistors. The paper divides the design of AVD into an absolute value extraction part and a comparator. The input (2’s complement) can be positive or negative numbers in the absolute value extraction part. By observing the most significant bit (MSB) of the input, the design can determine the sign of input and output magnitude. For the comparator, this paper uses a logic of step-by-step comparison from the most to the least significant bits. Then, this paper finds the minimum delay of the design by critical path analysis and gate sizing. The final delay is set at 1.5 times its minimum. Device voltage optimization is applied for calculating the energy consumption. Finally, with 1.5 times the minimum delay, the energy consumption is 40% less than the consumption when the delay is the minimum.

Geometric Programming Approach to Glitch Minimization via Gate Sizing

Geometric Programming Approach to Glitch Minimization via Gate Sizing

DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs

The objective of a leakage recovery step is to make use of positive slack and reduce power by performing appropriate standard-cell swaps such as threshold-voltage ( V th ) or channel-length reassignments. The resulting engineering change order netlist needs to be timing clean. Because this recovery step is performed several times in a physical design flow and involves long runtimes and high tool-license usage, previous works have proposed graph neural network–based frameworks that restrict feature aggregation to three-hop neighborhoods and do not fully consider the directed nature of netlist graphs. As a result, the intermediate node embeddings do not capture the complete structure of the timing graph. In this article, we propose DAGSizer , a framework that exploits the directed acyclic nature of timing graphs to predict cell reassignments in the discrete gate sizing task. Our DAGSizer (Sizer for DAGs) framework is based on a node ordering-aware recurrent message-passing scheme for generating the latent node embeddings. The generated node embeddings absorb the complete information from the fanin cone (predecessors) of the node. To capture the fanout information into the node embeddings, we enable a bidirectional message-passing mechanism. The concatenated latent node embeddings from the forward and reverse graphs are then translated to nodewise delta-delay predictions using a teacher sampling mechanism. With eight possible cell-assignments, the experimental results demonstrate that our model can accurately estimate design-level leakage recovery with an absolute relative error ε model under 5.4%. As compared to our previous work, GRA-LPO, we also demonstrate a significant improvement in the model mean squared error.

ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation

Modern electronic design automation flows depend on both implementation and signoff tools to perform timing-constrained power optimization through Engineering Change Orders (ECOs), which involve gate sizing and threshold-voltage ( V th )-assignment of standard cells. However, the signoff ECO optimization is highly time-consuming, and the power improvement is hard to predict in advance. Ever since the industrial benchmarks released by the ISPD-2012 gate-sizing contest, active research has been conducted extensively to improve the optimization process. Nonetheless, previous works were mostly based on heuristics or analytical methods whose timing models were oversimplified and lacked of formal validations from commercial signoff tools. In this article, we propose ECO-graph neural networks (GNN), a transferable graph-learning-based framework, which harnesses GNNs to perform commercial-quality signoff power optimization through discrete ( V th -assignment. One of the highlights of our framework is that it generates tool-accurate optimization results instantly on unseen netlists that are not utilized in the training process. Furthermore, we propose a subgraph approximation technique to improve training and inferencing time of the proposed GNN model. We show that design instances with non-overlapping subgraphs can be optimized in parallel so as to improve the inference time of the learning-based model. Finally, we implement a GNN-based explanation method to interpret the optimization results achieved by our framework. Experimental results on 14 industrial designs, including a RISC-V-based multi-core system and the renowned ISPD-2012 benchmarks, demonstrate that our framework achieves up to 14× runtime improvement with similar signoff power optimization quality compared with Synopsys PrimeTime , an industry-leading signoff tool.

Task-Based Parallel Programming for Gate Sizing

Physical synthesis engines need to embrace all available parallelism to cope with the increasing complexity of modern designs and still offer high quality of results. To achieve this goal, the involved algorithms need to be expressed in a way that facilitates fast execution time across a range of computing platforms. In this work, we introduce a task-based parallel programming template that can be used for speeding up timing and power optimization. This approach utilizes all available parallelism and enables significant speedup relative to custom multithreaded approaches. Task-based parallelism is applied to all parts of the optimization engine covering also parts that are traditionally executed serially for preserving maximum timing accuracy. Using Taskflow as the parallel programming and execution engine, we achieved a speedup of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8\times $ </tex-math></inline-formula> for gate sizing optimizations on the ISPD13 benchmarks with marginal extra leakage power relative to state-of-the-art multithreaded gate sizers. This result was supported by two dynamic heuristics that restrict the number of examined gate sizes and simplify local timing updates. Both heuristics tradeoff additional runtime reduction with marginal leakage power increases.

Optimized Design of a 4-bits Absolute-Value Detector

4-bits Absolute Value Detector circuit is a very commonly used circuit design. As to simplify the internal circuit design to make the total number of stage lesser which provides a less critical path circuit delay. Generally, this paper used combination of static CMOS design and the path transistor circuit design to design our circuit. After we got the optimized design, we applied the logic effort calculation to calculate the minimum delay of the circuit and determined the specific gate sizing value for each logic component. The energy optimization can be obtained by increasing our delay and adjusting the power supply (VDD) value. Eventually, we sacrifice our delay a little bit to get a huge amount of energy reduction.

A 42.4 FO4 (1V), 19.27 Eu (1V) 4-bit Absolute-Value Detector

Absolute-value detector (AVD) is a fundamental arithmetic logic circuit widely applied in spike-sorting area. In this paper, a novel circuit design of a concise 4-bit AVD whose topology consists of a 2’s complement circuit and a 3-bit ripple carry adder (for comparison purpose), etc., with critical path designed to be as short as possible. Since the minimum energy consumption and the minimum delay cannot be guaranteed at the same time, critical path gate sizing is conducted. Using the method of logic effort and appropriately relaxing the delay requirements to 1.5 times the minimum value, a suitable voltage ranging from 0V to 1V is found to achieve the goal of minimum power consumption.

Design and Optimization of 4-bit Absolute-value Detector Based on CMOS

With the development of neural signal acquisition systems, spike-sorting algorithms have been paid full attention. As one of the most extensively used spike-detection algorithms, a 4-bit absolute-value detector is designed in the paper, which comprises three types of architecture. The first design is using combinational logic circuit through a truth table of the absolute value of 2′s complement format and a comparator; the second design is a combination of a series of half adders and transmission gates and a comparator; the third design consists of a combinational logic circuit by truth table of 2′s complement and a cascade of full adders. Then the paper compares the total number of stages and consuming transistors of each circuit, and finally chooses the second circuit, which has five stages and 74 transistors of consumption, as the object of following optimization of critical path delay and energy consumption. With gate sizing, the optimized critical path delay is about 43.05 tp0. The original energy consumption under minimum delay is 49.88C, and the optimized energy consumption under 1.5x minimum delay is 30.35C which is reduced by 39.16%. The processing of the functional realization and circuit optimization of absolute-value detectors can both benefit from the design presented in this work.

Single Event Transient on Combinational Logic: An Introduction and their Mitigation

Single event transients pose a major threat to the reliability of modern VLSI designs. Improving the robustness of combinational logic is challenging due to its complexity, masking effects, and signal dependence. This paper presents the mechanisms and concepts of SET generation, modeling, masking, and propagation in combinational logic. It also discusses design parameters and their impact on circuit robustness. An overview of automated design strategies for radiation hardening by design and their advantages and disadvantages is provided, covering gate sizing, gate duplication, gate remapping, load increase, layout spacing, and charge sharing techniques.

Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

As CMOS devices become smaller, aging-induced and process variations become major issues for circuit reliability. In this paper, a statistical gate sizing method is proposed to improve the lifetime reliability of manufactured chips in the presence of process variations and aging effects. To this end, we propose a canonical first order delay model to estimate the delay degradation of a gate under negative bias temperature instability and process variations considering spatial correlations. Using the proposed gate delay model, a statistical static timing analysis method is introduced to compute the circuit delay considering the joint effect of process variation and negative bias temperature instability. To guarantee that the circuit meets the required timing constraints, we propose an incremental gate sizing technique. This technique first computes the criticality of each gate defined as the probability that a gate lies on the critical path due to negative bias temperature instability and process variations. Then, a group of gates with the highest ranking according to criticality is chosen for a gate sizing-based timing optimization. It is worth nothing that, by using the proposed statistical gate delay model, we can compute the criticality of each gate incrementally. Experimental results based on ISCAS’85 benchmark circuits show that the proposed method can improve the lifetime reliability defined as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1(\mu + 3\sigma)$ </tex-math></inline-formula> of the initial delay distribution of the circuit at the expense of 8.64% area overhead. In comparison with the path-based method, the proposed approach is much faster, especially for larger circuits, which makes it a viable solution to optimize the lifetime reliability of very large-scale circuits used in industry.

Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs

Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations (PVs) and aging effects manifest themselves as gate delay shifts, which in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this article, we present a systematic methodology for analyzing a VLD circuit and identifying critical one-cycle and two-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is proposed. Our objective is, in a less pessimistic fashion, to make constructed VLD circuits better (less vulnerable to timing variability). The experimental results show that the proposed framework can generate extra timing margins for VLD, such that process-induced error rate can be reduced to 0%-0.1% under 10% variability in gate delay. On average, an extra timing margin of 11.48% can be obtained without lengthening the clock period, and 1.52% area can be reduced simultaneously.

Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage Assignment

Timing closure remains one of the most critical challenges of a physical synthesis flow, especially when the design operates under multiple operating conditions. Even if timing is almost closed at the end of the flow, last-mile placement and routing congestion optimizations may introduce new timing violations. Correcting such violations needs minimally disruptive techniques such as threshold voltage reassignment and gate sizing that affect only marginally the placement and routing of the almost finalized design. To this end, we transform a powerful Lagrangian-relaxation-based optimizer, used for global timing optimization early in the design flow, into a practical incremental timing optimizer that corrects small timing violations with fast runtime and without increasing the area/power of the design. The proposed approach was applied to already optimized designs of the ISPD 2013 benchmarks assuming that they experience new timing violations due to local wire rerouting. Experimental results show that in single corner designs, timing is improved by more than 36% on average, using 45% less runtime. Correspondingly, in a multicorner context, timing is improved by 39% when compared to the fully-fledged version of the timing optimizer.

Improved Design of a 4-bit Absolute-Value Detector Using Simplified Chain Carry Adder

4-bit absolute-value detector (AVD), as one of the basic implementations of bit arithmetic with logic circuits, can help grab a better understanding about digital integrated circuits. Conventional 4-bit AVDs scheme in a multi-comparator and multiplexers, or need to consider multiple situations of overflow and carry-in, both of which could make the final circuit to be complex, labyrinthine and inefficient in the meantime. In this paper, a new design of 4-bit AVD is proposed, the topology of which includes a 2’s complement calculator and a specially designed logic circuit known as chain carry adder (CCA). The whole circuit is concise and the critical path is rigorously considered to make it as short as possible. The delay is set to 1.5 times its minimum, which is positively corresponding to the length of the critical path, the energy accordingly reaches its lower limit. Gate sizing and Device Voltage (VDD) optimization are proceeded for the exact purpose of proving that the circuit energy is minimized.