A 42.4 FO4 (1V), 19.27 Eu (1V) 4-bit Absolute-Value Detector

Abstract

Absolute-value detector (AVD) is a fundamental arithmetic logic circuit widely applied in spike-sorting area. In this paper, a novel circuit design of a concise 4-bit AVD whose topology consists of a 2’s complement circuit and a 3-bit ripple carry adder (for comparison purpose), etc., with critical path designed to be as short as possible. Since the minimum energy consumption and the minimum delay cannot be guaranteed at the same time, critical path gate sizing is conducted. Using the method of logic effort and appropriately relaxing the delay requirements to 1.5 times the minimum value, a suitable voltage ranging from 0V to 1V is found to achieve the goal of minimum power consumption.