Gate-oxide Reliability Issue Research Articles

[formula omitted] IO buffer with [formula omitted] devices considering hot-carrier and gate-oxide reliability issues

This paper presents circuit for 2×VDD signaling I/O buffer to solve the gate-oxide and hot-carrier reliability issues without consuming any active static power. The design is verified for a range of loads varying from 4 pF to 200 pF with operating speed ranging from 12 Mbps to 500 Mbps. The proposed circuit is implemented in 16 nm FinFET technology using 1.8 V thick gate devices. The design can be used in any CMOS technology for 2×VDD signaling I/O buffer to reduce hot-carrier effect and to avoid gate-oxide reliability issues.

High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode

Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET.

Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability

This paper presents a [Formula: see text] tolerant I/O buffer with low voltage (VDD) devices. A novel bootstrap circuit for mixed voltage I/O buffer is proposed to solve the unwanted leakage paths and gate oxide reliability issues. The proposed circuit is designed using 1.8[Formula: see text]V thick gate devices in 22-nm FinFET technology with 1.8[Formula: see text]V signaling and tolerant to 3.3[Formula: see text]V. The structure can be used in any CMOS technology for [Formula: see text] tolerant I/O buffer.

Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

In the implanted biomedical devices, the silicon chips with monopolar stimulation design have been widely applied. To protect the negative-voltage pins of the implanted silicon chip from the electrostatic discharge (ESD) damage, the ESD protection circuit should be carefully designed to avoid any wrong current path under normal circuit operation with the negative voltage. In this article, a new power-rail ESD clamp circuit for the application with an operating voltage of −6 V has been proposed and verified in a 0.18- $\mu \text{m}$ 3.3-V CMOS process. The proposed circuit, realized with only 3.3-V nMOS/pMOS devices, is able to prevent the gate-oxide reliability issue under this −6-V application. With the proposed ESD detection circuit, the turn-on speed of the main ESD clamp device, which is a stacked-nMOS (STnMOS), can be greatly enhanced. The STnMOS with a width of $400~\mu \text{m}$ can sustain over 8-kV human body model (HBM) ESD stress and perform low standby leakage current of ~5.4 nA at room temperature under the circuit operating condition with −6-V supply voltage.

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.

This paper presents a 4 × VDD neuro-stimulator in a 0.18- μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000- μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

Gate Oxide Reliability Issues of SiC MOSFETs Under Short-Circuit Operation

Silicon-Carbide (SiC) MOSFETs, due to material properties, are designed with smaller thickness in the gate oxide and a higher electric field compared to Si MOSFETs. Consequently, the SiC MOSFETs have a worse reliability which causes higher leakage currents during instantaneous abnormal operating conditions. This paper investigates the reliability issues of the SiC MOSFET gate oxide under standard short-circuit test conditions. In this paper, 1200-V SiC MOSFETs are newly modeled, and also their short-circuit sustainability (tolerance) have been studied at different drain-source and gate-source voltages. A hardware tester circuit was designed and developed to test the devices under such extreme circuit conditions. Then, the gate reliability of SiC MOSFET devices have been compared to that of Si power devices of similar ratings. The results reveal a higher reduction in the instantaneous gate-source voltage of SiC MOSFETs compared to that of Si devices under the same operating conditions. The gate-voltage reduction phenomenon results from the higher leakage currents through the gate. Furthermore, it was found that the gate-source voltage reduction during the test depends on the gate structures. The gate voltage reduction of SiC MOSFETs with planar gate is higher than that of MOSFETs with shield planar gate. As the pulse duration increases in short-circuit tests, the leakage current in the gate-source of SiC devices increases. The results show that even though the SiC MOSFETs are very capable of processing long pulses and high power in the drain-source, the gate-source side is highly degraded by these pulses in the test. Moreover, whenever a small number of the short-circuit tests are applied, the gate structure of SiC MOSFETs becomes broken while the drain-source is still able to block the dc-link voltage. The paper concludes that the short-circuit reliability of the gate was found to be worse compared with commercial Si devices with similar rating.

A Solution Toward the OFF-State Degradation in Drain-Extended MOS Device

We investigated the surface band-to-band tunnelling (BTBT) current under the off-state condition in drain-extended MOS (DeMOS) devices. We found significant gate-induced drain leakage current due to surface BTBT, which was also reported earlier as the dominant cause of early time-dependent dielectric breakdown and device failure. Furthermore, a layout solution for the existing DeMOS device is proposed in order to mitigate the surface BTBT current and the associated gate oxide reliability issues, without sacrificing the mixed-signal performance of the device.

NLDD/PHALO-Assisted Low-Trigger SCR for High-Voltage-Tolerant ESD Protection Without Using Extra Masks

A new silicon-controlled rectifier (SCR) is proposed and realized in the foundry's 0.18-mum CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or trigger circuits, the new n-type lightly doped drain and p-type halo-assisted SCR has a trigger voltage Vt1 as low as 7 V and an ESD robustness exceeding 50 mA/mum, which enables effective ESD protection. Compared with the traditional low-voltage-triggered SCR, the new structure not only has a lower trigger voltage but also is more suitable for high-voltage-tolerant applications avoiding any gate-oxide reliability issue.

Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology

In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to provide higher operating speed with lower power supply voltage. However, regarding compatibility with the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes face the gate-oxide reliability problems in the interface circuits due to the voltage levels higher than normal supply voltage (1× VDD) required by earlier applications. As a result, mixed-voltage I/O circuits realized with only thin-oxide devices had been designed with advantages of less fabrication cost and higher operating speed to communicate with the circuits at different voltage levels. In this paper, two new mixed-voltage-tolerant crystal oscillator circuits realized with low-voltage CMOS devices are proposed without suffering the gate-oxide reliability issues. The proposed mixed-voltage crystal oscillator circuits, which are one of the key I/O cells in a cell library, have been designed and verified in a 90-nm 1-V CMOS process, to serve 1-V/2-V tolerant mixed-voltage interface applications.

New low-voltage small-area mixed-voltage I/O buffer

A new mixed-voltage I/O buffer having the characteristics of low-voltage operation and small-area realization is proposed. The proposed I/O buffer provides significantly reduced latency at low supply voltages by eliminating the voltage swing degradation at timing-critical nets. The buffer also provides smaller layout area by avoiding the use of dedicated extra circuits like dynamic gate-bias circuit (DGBC) and hot-carrier prevention circuits (HCPC) to cope with hot-carrier-induced gate-oxide reliability issue. Comparison results in an 80-nm CMOS process indicate that the proposed mixed-voltage I/O buffer achieves 73% reduction on buffer latency, 23% reduction on operating voltage, and 31% reduction on layout area as compared to conventional I/O buffers.

PLDD/NHALO-assisted low-trigger SCR for high-voltage tolerant ESD protection in foundry CMOS process without extra mask

A new semiconductor-controlled rectifier (SCR) is proposed and realised in the foundry 0.18 µm CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or trigger circuits, the new p-type lightly-doped-drain and n-type halo (NHALO) assisted SCR has a trigger voltage as low as 7 V and an ESD robustness exceeding 50 mA/µm to provide an effective protection. Compared with traditional LVTSCR, the new structure not only has a lower trigger voltage, but can also be more suitable for high-voltage tolerant applications without the gate-oxide reliability issue.

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> , negative-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> , positive-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD,</sub> and negative-to-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.

10 kV, 87 mΩcm&lt;sup&gt;2&lt;/sup&gt; Normally-Off 4H-SiC Vertical Junction Field-Effect Transistors

SiC JFET, compared with SiC MOSFET, is attractive for high power, high temperature applications because it is free of gate oxide reliability issues. Trenched-and-Implanted VJFET (TIVJFET) does not require epi-regrowth and is capable of high current density. In this work we demonstrate two trenched-and-implanted normally-off 4H-SiC vertical junction field-effect transistors (TI-VJFET), based on 120μm, 4.9×1014cm-3 and 100μm, 6×1014cm-3 drift layers. The corresponding devices showed blocking voltage (VB) of 11.1kV and specific on-resistance (RSP_ON) of 124m7cm2, and VB of 10kV and RSP_ON of 87m7cm2. A record-high value for VB 2/RSP_ON of 1149MW/cm2 was achieved for normally-off SiC FETs.

Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique

An nMOS-blocking technique for mixed-voltage I/O buffer realized with only 1timesVDD devices can receive 2timesVDD , 3timesVDD, and even 4timesVDD input signal without the gate-oxide reliability issue is proposed. In this paper, the 2timesVDD input tolerant mixed- voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.25-mum 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3timesVDD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.13-mum 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed nMOS-blocking technique can be extended to design the 4timesVDD , 5timesVDD, and even 6timesVDD input tolerant mixed-voltage I/O buffers. The limitation of the nMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit

Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface

A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using a thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35 /spl mu/m CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 /spl mu/m can be obviously improved from the original /spl sim/2 kV to be greater than 8 kV by this SNTSCR device with device dimensions of only 60 /spl mu/m/0.35 /spl mu/m.