Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability

Abstract

This paper presents a [Formula: see text] tolerant I/O buffer with low voltage (VDD) devices. A novel bootstrap circuit for mixed voltage I/O buffer is proposed to solve the unwanted leakage paths and gate oxide reliability issues. The proposed circuit is designed using 1.8[Formula: see text]V thick gate devices in 22-nm FinFET technology with 1.8[Formula: see text]V signaling and tolerant to 3.3[Formula: see text]V. The structure can be used in any CMOS technology for [Formula: see text] tolerant I/O buffer.