Gate Oxide MOSFETs Research Articles

SiC MOSFET Gate Oxide Quality Improvement Method in Furnace Thermal Oxidation with Lower Pressure Control

We have investigated carbon behavior resulting from pressure control in furnace thermal oxidation process and evaluated the effect on gate oxide quality resulting from this pressure control. In order to investigate the potential reduction of carbon defects by reducing CO and CO2, an analysis of oxidized SiC wafers was conducted. To evaluate the effect of pressure control related carbon component change during thermal oxidation, QBD characteristic was evaluated in SiC MOS Capacitance. The analysis results revealed on observable decrease in carbon at the SiO2/SiC interface and the SiO2 layer. The QBD results shown that improved at lower pressure better than those obtained in the general pressure.

Mobile ions entering the IGBT gate oxide - electrical detection and failure localization by lock-in thermography

Small mobile ions, especially sodium and potassium are known to have the ability to infiltrate and move within gate oxide layers of silicon MOS devices. The ion transport in silicon oxide is either a temperature-driven, isotropic diffusion process, or an electrical ion current in presence of an electric field. Therefore, the high temperature gate bias test with negative polarity provides ideal conditions to identify the presence of mobile ions in the gate oxide of IGBT and MOSFET. Mobile ions in sufficient concentration can severely affect the electric characteristics, such as the turn-on and turn-off behavior of the MOS channel, by creating a shift in the gate threshold voltage or excessive sub-threshold currents. This paper shows several examples of how mobile ions can get into the gate oxide, e.g., via cracks in top side metallization, or by corrosive attack of cap layers. All these different failure modes develop the same electrical failure signature after temperature and/or gate bias stress. During the investigations on mobile ions, a special lock-in thermography method was developed that allows to localize the defect sites in the semiconductor by taking advantage of exclusive excitation of MOS cells affected by mobile ion contamination. Finally, after defect localization, further analytical methods can be applied to identify the exact nature of the access path to the gate oxide. Based on the test and analytical routine described above, a special test method was developed that allows to evaluate the permeability of the semiconductor chip top side structures towards mobile ions and to check for weak spots and potential leakage paths.

Enhanced EBAC localization of gate oxide defects after high voltage electron beam irradiation

Electron Beam (EB) irradiation with high acceleration voltage is widely reported to have resulted in significant degradation on transistor parametric performances. Therefore, high voltage EB should be avoided during nanoprobing transistor device characterization. There are many studies that mainly emphasize on prevention, cause, and consequences of such detrimental effects but rarely focus on the exploitation of these EB effects. In fact, high voltage EB could possibly leverage to enhance nanoscale fault isolation. In this paper, it was discovered that high voltage EB effects can be utilized to enhance the EBAC localization of Gate Oxide breakdown defects. Three successful case studies are described to demonstrate these enhancements on P-type and N-type MOSFET gate oxide defect isolation through the suppression on the gate leakage by high voltage EB induced charge trapping mechanism.

An in-depth investigation of gate leakage current degradation mechanisms in 1.2 kV 4H-SiC power MOSFETs

In this paper, a comprehensive study on the forward and reverse current degradation mechanisms in 1.2 kV planar SiC MOSFETs are investigated. With the help of Sentaurus TCAD simulations, numerical fitting method, step-bias stress, current-voltage (I-V) and capacitance-voltage (CV) experiments, we proposed defect-related transport models to describe the progression of gate leakage currents under forward and reverse high biases. It is found that, (1) trap-assisted tunneling (TAT) and Fowler-Nordheim (FN) tunneling dominate the forward low and high current transport process respectively. Moreover, the holes trapping is mainly responsible for the degradation of gate oxide and premature breakdown of SiC MOSFETs; (2) the reverse leakage current under high electric field is mainly carried by FN tunneling electrons, which lead to an increase of the intermediate localized states distributed in the SiC/SiO2 interface.

Physical mechanisms for gate damage induced by heavy ions in SiC power MOSFET

The objective of the paper is to present a trap assisted conduction mechanism able to explain the creation of a conductive path in the gate oxide of SiC power MOSFET during the impact of heavy ions. The consequent large current flow through the oxide can induce damages to the gate structure. The proposed mechanism combines a Fowler-Nordheim tunneling at the SiC/SiO2 interface with a trap-assisted valence band conduction mechanisms based on Poole-Frenkel effect. The model is based on the results of 2D finite element simulation and is supported by previous works dealing with trap assisted tunneling hole injection in silicon dioxide.

High Temperature Gate Voltage Step-by-Step Test to Assess Reliability Differences in 1200 V SiC MOSFETs

In this paper, robustness and reliability differences related to the performance of the gate oxide of commercially-available 1200 V-rated planar and trench SiC MOSFETs have been investigated. Due to a thin gate oxide in SiC MOSFETs and to a naturally imperfect interface of the oxide layer (SiO2) with the SiC material, its quality and reliability become very important and could be a limiting factor of the SiC technology when compared to the Si one. A dedicated gate oxide step-by-step (VG SbS) tester has been prepared during which the gate voltage is varied with different profiles. Results of Fowler-Nordheim (FN), Time Dependent Dielectric Breakdown (TDDB) and three test runs of the VG SbS are presented in this paper. Both technologies show good reliability figures to allow the use in the application. Trench technology shows higher robustness limits whereas the extrapolated reliability at the rated gate voltage is superior for the planar one.

Online Detection of MOSFET Gate Oxide Degradation in a Three-Phase Inverter-Drive Application

Failure in electrical machines or their drives can be catastrophic in safety-critical applications. Both silicon and silicon-carbide MOSFETs experience gate oxide degradation that leads to device failure. It is ideal to detect gate oxide degradation early using noninvasive, online techniques. In this article, an online gate oxide degradation detection method is proposed to reduce the reliability concern of using MOSFET switching devices. Gate oxide degradation causes a delay in phase current rise. Although the delay is short, it affects the voltage commands calculated in the controller. It is shown through analysis, simulation, and experiment that space vector pulsewidth modulation (SVPWM) duty cycle commands reflect the delay in phase current rise caused by gate oxide degradation.

Oxide Edge Trap Density Extraction in Silicon Nanowire MOSFET From Tunnel Current Noise Measurement in Gated Diode Like Arrangement

Edge traps in the gate oxide of silicon nanowire MOSFETs have been extracted from tunnel current noise measurement in a gated diode like arrangement. We have found that, low frequency noise in tunnel current results from collective response of the edge traps available within the gate oxide surrounding band-to-band generation (BTBG) region of silicon nanowire, and when the BTBG region is accessed by favorable terminal biases. From detail modeling of the phenomenon, we derived a closed form expression of the tunneling current noise power spectral density (PSD) employing which oxide edge trap density in nanowire MOSFET had been extracted through its fit with the experimental noise PSD data. We furthermore validated our model for different BTBG biases, and contrasted our result with the bulk oxide trap density in identical MOSFET, while the latter was separately estimated from the gate current noise PSD measurement. Mismatch between the oxide bulk trap and edge trap concentrations has been found, whereby actual edge trap density remains otherwise hidden from the widely employed gate current noise measurement technique. It is because, the present scheme improves the resolution of the extracted oxide edge trap concentration in surrounded gate MOSFET owing to constricted tunnel current flow near the corner of the gate which imposes selectivity on the oxide edge traps

Effect of Gate-Oxide Degradation on Electrical Parameters of Silicon Carbide MOSFETs

Although gate-oxide degradation occurs in both silicon (Si) and silicon carbide (SiC) MOSFETs, it requires a special attention in SiC MOSFETs. This is because the gate oxide in SiC MOSFETs is comparatively thinner than the gate oxide in Si MOSFETs, and thus, a higher electric field that appears across it could push the gate oxide to its reliability limit. While several electrical parameters have been identified as precursors (indicators) for monitoring the gate-oxide degradation process in Si MOSFETs, very few have been identified for their SiC counterparts. The purpose of this article is twofold. The first objective is to demonstrate that the three gate-oxide degradation precursors identified for Si MOSFETs: 1) threshold voltage, 2) gate-plateau voltage, and 3) gate-plateau time can also be extended to SiC MOSFETs. The second objective is to demonstrate analytically and experimentally that all three precursors increase in a linear-with-log-stress-time manner during gate-oxide degradation in both planar and trench-gate SiC MOSFETs. The increasing trends of precursors and their associated logarithmic time responses were experimentally verified by inducing accelerated gate-oxide degradation in two different commercial SiC MOSFETs (650-V, 70-A trench-gate MOSFETs and 1200-V, 19-A planar MOSFETs) under high temperatures of 150 and 125 °C, respectively.

Total-Ionizing-Dose Effects on 3D Sequentially Integrated, Fully Depleted Silicon-on-Insulator MOSFETs

Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency (1/f) noise measurements are compared for (1) conventional planar FD-SOI MOSFETs, and (2) MOSFETs formed in the bottom layer of the 3D process and subjected to the process steps associated with formation of a second active layer. Similar radiation-induced voltage shifts and increases of 1/f noise are observed after irradiation for both types of structures. These similar changes in response show that the additional thermal processing involved with 3D fabrication has little effect on border-trap densities and radiation-induced charge trapping in gate and/or buried oxides of MOSFETs formed in the bottom layer of the 3D process.

Direct Epitaxial Growth of Polar (1 - x)HfO2-(x)ZrO2 Ultrathin Films on Silicon.

Ultrathin Hf1–xZrxO2 films have attracted tremendous interest since they show ferroelectric behavior at the nanoscale, where other ferroelectrics fail to stabilize the polar state. Their promise to revolutionize the electronics landscape comes from the well-known Si compatibility of HfO2 and ZrO2, which (in amorphous form) are already used as gate oxides in MOSFETs. However, the recently discovered crystalline ferroelectric phases of hafnia-based films have been grown on Si only in polycrystalline form. Better ferroelectric properties and improved quality of the interfaces have been achieved in epitaxially grown films, but these are only obtained on non-Si and buffered Si(100) substrates. Here, we report direct epitaxy of polar Hf1–xZrxO2 phases on Si, enabled via in situ scavenging of the native a-SiOx layer by Zr (Hf), using pulsed laser deposition under ballistic deposition conditions. We investigate the effect of substrate orientation and film composition to provide fundamental insights into the conditions that lead to the preferential stabilization of polar phases, namely, the rhombohedral (r-) and the orthorhombic (o-) phases, against the nonpolar monoclinic (m-), on Si.

Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell

The battery-powered mobile devices limited energy process by MOSFET's due to subthreshold swing and underneath 60mV/dec for ultra fewer energy applications. This research introduces the layout and execution of a mobile electronic device full-on-presence, extended Miller potential, and reduced HETT subthreshold swing effectiveness has been compared with MOSFET's Gate oxide blending on source can increase channel tunneling in this work. To enhance transistor line, Miller capacitance impact can be decreased by using low band offset equipment and small power product of metals such as Ge or SiGe. This, in turn, leads to stronger transistor efficiency features. The proposed layout and execution of HETT includes manufacturing of mutually NHETT and PHETT and efficiency analyzes of both NHETT and PHETT. Concerning the fundamental and skeletal distinctions among MOSFET and HETT to promote the utilization of MOSFET instead of HETT, the benefits and constraints of both NHETT and PHETT have been detailed. HETT's construction process is by no means entirely different, suitable for the scheme of MOS method and suitable for transportable motorized applications. HETT provides the 6T SRAM cell electricity evaluation and the output was reviewed using standard SRAM cell. The average power, maximum power and minimum power of SRAM by using both MOSFET and HETT are obtained and compared. The mask layers of HETT fabrication is not that much difference than MOSFET and hence CMOS MOSFET fabrication is friendly to HETT fabrication. In future, the combination of both CMOS MOSFET and HETT are used, CMOS technology for digital logic and HETT for semiconductor memory applications.

Design and simulation on improving the reliability of gate oxide in SiC CDMOSFET

For silicon carbide (SiC) power MOSFETs, gate oxide reliability under high electric stress leading to device failure has become one of the major concerns in actual applications. In this paper, a novel SiC MOSFET with center dielectric layer (CDMOSFET) is proposed to improve the gate oxide robustness. Comparisons of the electric field in gate oxide layer and dielectric layer between CDMOSFETs and conventional SiC MOSFETs have been carried out through the TCAD Silvaco. Numerical simulation results indicate that the peak electric field in gate oxide decreases ~30% (1.1 MV/cm) compared with conventional SiC MOSFETs at breakdown of 2.9 kV. Furthermore, the influence of dielectric layer configuration, including width, thickness and depth, on the reliability of the gate oxide layer is further discussed in detail. The results illustrate that the peak electric field in gate oxide layer is reduced via employing the dielectric layers in the JFET region of MOSFETs owing to the decrease of impact ionization generation rate and perpendicular electrical field along the SiC/SiO2 interface, thus improving the reliability of the gate oxide of SiC MOSFETs.

6MV LINAC characterization of a MOSFET dosimeter fabricated in a CMOS process

This paper presents the characterization of a thick gate oxide MOSFET for radiotherapy in-vivo dosimetry. The device is an N-channel transistor fabricated in a standard CMOS process using the Field Oxide as gate insulator. Sensitivity, fading, gate bias voltage dependence, percentage depth dose and angular response were assessed using a 6 MV LINAC. Experimental results showed that it is possible to estimate dose with a 3% uncertainty in a range up to 85 Gy with an average sensitivity of 62 mV/Gy. The measurement system noise equivalent dose is 3 mGy.

Online Condition Monitoring of Power MOSFET Gate Oxide Degradation Based on Miller Platform Voltage

The condition monitoring problem of power devices is significant for diagnostics and prognostics of a switched-mode power supply (SMPS) system. For power mosfet , the gate oxide degradation often occurs in various applications. However, there is no online condition monitoring method for gate oxide degradation so far. In this paper, a new precursor that can be used for online condition monitoring of power mosfet gate oxide degradation is proposed. Gate oxide degradation mechanisms and effect are summarized, and the mosfet turn-on process is analyzed. Then, a theoretical model is established to describe the relationship between miller platform voltage and two types of gate oxide defects, and miller platform voltage is identified as a new precursor. The precursor can be extracted without impacting system operation, thus online condition monitoring can be accomplished. The accelerated degradation test is carried out for power mosfet s with both high electric field and gamma irradiation methods, and the degraded devices injection and in situ monitoring of miller platform voltage are conducted on a BOOST circuit to verify the feasibility of the new precursor. Experimental results demonstrate that the new precursor can be applied to online condition monitoring of power mosfet gate oxide degradation in the SMPS system.

(Dielectric Science and Technology Division Thomas D. Callinan Award Address) Dielectrics for MOS Integrated Circuits

In this paper author’s historical 45 year works for the development of the dielectrics for MOS Integrated Circuits are described as an invited talk as the recipient of 2017 ECS DS&T Thomas D. Callinan Award. Dielectric films has been the key components of the MOS LSI’s since its beginning. The author’s contributions include introduction of BPSG reflow technique into NMOS LSI technology, the finding of plasma induced damage to the gate oxide during ion implantation and reactive ion etching the introduction of RTN gate oxide to prevent the boron penetration, the introduction of direct-tunneling gate oxide for CMOS logic devices, and the demonstration of the 0.4 nm EOT Lasilicate gate oxide MOSFETs.

(Invited) Hot Carrier Reliability of High Voltage HVMOSFETs in BCD (Bipolar-CMOS-DMOS) Technology

This paper discusses three important issues in hot carrier (HC) reliability of LDMOSFET ((Laterally Diffused MOSFETs) in BCD technology. One of the main reliability issues encountered during development of the LDMOSFET is optimizing the trade-offs between specific on-resistance (Rdson) and hot carrier (HC) degradation [2]. For instance, Rdson can be reduced by increasing the drift region doping concentration or shrinking the drift region length. Both of these changes result in higher lateral electric field in the drift region which lead to increased HC degradation. The second issue is how to reduce HC degradation in LDMOS due to Back-End-Of-Line (BEOL). It has been reported for CMOS devices that HC performance can be degraded by BEOL processes such as interlayer dielectric film deposition, etch, metal deposition and etch process [3, 4]. The BEOL processes in BCD technology may have a worse impact on LDMOS HC performance than on CMOS’s since it has such as higher energy implants and thicker metal deposition and etch. The third issue is the influence of self heating on the measurement of HC degradation in high gate voltages stress for HC SOA (safe-operating-area) in high voltage LDMOS [5, 6]. To address the first issue, we have compared the thin gate oxide (11.5nm) and thick gate oxide (60nm) LNDMOS hot carrier degradation results as shown in Fig.1 (b). The HC degradation has been significantly reduced in thick gate oxide LNDMOS. The main reason for the reduction may be due to drift region oxide thickness. Based on the results, we proposed a new LDMOS structure in a BCD technology that improves HC degradation without sacrificing the device breakdown voltage or Rdson [1]. The process to form the thick oxide in drift region-I in the LNDMOS is the same as to form thick gate oxide MOSFET, so only a layout change is required. The 11.5nm gate oxide thickness in the channel region remains the same for both LNDMOS structures. The maximum lateral electric field Emax in drift region-I would be reduced by over 94% if the oxide thickness increased to 60nm from 11.5nm based on our calculation. TCAD simulations clearly show that impact ionization rate for the 30V LNDMOS with the thick oxide in drift region-I has been significantly reduced, and also its peak location has been pushed away from the surface into the bulk of the silicon within drift region-I as shown in Fig.2(b). For the second issue, we demonstrated a modified SiN barrier layer which can improve device hot carrier performance in the LDMOSFET. We show experimentally that using a barrier layer of SiN or SiON which is engineered to have a relatively high refractive index (RI) and electrical conductivity can reduce the BEOL effect on hot carrier performance. Increasing the SiH4 flow rate during deposition increases the film’s RI and also its electrical conductivity [9]. The increased electrical conductivity of the SiN barrier layer allows charge from plasma processing to be dissipated into the silicon. At 4000C, a typical BEOL dielectric deposition temperature, the conductivity of the SiN barrier layer is much higher. Thus, the SiN barrier layer can reduce the PPID for the oxide in drift region resulting in reduced HC degradation. The HC Idlin degradation for the LNDMOS device with thick oxide in drift region and high RI SiN or SiON barrier layer has been significantly reduced to less than 1/3 the degradation observed in the standard LNDMOS as shown in Fig.2 (a). The reduced HC Idlin degradation is about 68% due to the thick oxide in drift region-I, and about 32% from the high RI SiN barrier layer. The HC Vth (threshold voltage) degradation exhibited very small degradation after the HC stress. Our data shows self heating, caused by HC stress in the thick gate oxide HV LNDMOS, significantly affected Idlin/Rdson electrical parameter and HC degradation characteristic. The change in delay time between the removal of the HC stress after each stress cycle and the parameter measurement resulted in a significant difference in HC Idlin/Rdson degradation [6]. For a longer delay time, lower Idlin degradation was observed, see Fig.3 (a). The difference or recovery of degradation was mainly due to the self heating effect from Idlin degradation vs junction temperature change (Fig3.(b)) and temperature monitor data. The Idlin degradation from self heating effect seems to be more than from HC effect in packaged HV LNDMOS. In the final paper, we will include some methods to eliminate the self heating effect, and to separate the self heating and local HC injection effect. Figure 1

(Dielectric Science and Technology Division Thomas D. Callinan Award Address) Dielectrics for MOS Integrated Circuits

Introduction Insulator films are one of the fundamental elements of the semiconductor integrated circuits together with semiconductor substrate/films and metal/silicide interconnects. Functions of the insulator films in ICs (Integrated Circuits) are roughly classified into the following 6 categories; a) isolation between active devices, b) gate insulator of MOSFETs/MOS capacitors/MIM (Metal Insulator Metal) capacitors, c) sidewall insulation films for gate electrode, d) interlayer isolation films for interconnects, e) passivation films above the interconnects to cover and protect the IC chip surface, and f) insulator film between surface Si layer and Si substrate in SOI (Silicon On Insulator) wafer. In this paper, author’s past works related to the insulator films used ICs are reviewed. Introduction of BPSG reflow technique into NMOS LSI technology One of the severe problems for ICs until the middle of 1970’s was the disconnection of the aluminum interconnects at the steps of insulation film over the edges of poly Si lines and field SiO2 regions. The author applied BPSG (BoroPhospho Silicate Glass) reflow technique for the first time in the world to his developed NMOS LSI technologies in Toshiba, making the steps completely smooth, verifying the yield, and long term reliability in the 1k bit SRAM products in 1975. Finding of plasma induced damage to the gate oxide during ion-implantation and reactive ion etching The author developed a 64k bit DRAM technology from late 1970’s to the beginning of 1980’s. The introduction of source/drain heavy ion-implantation and RIE (Reactive Ion Etching) techniques of poly Si gate electrodes (2nd poly Si) were necessary to fabricate the designed small cell size. The accumulated ionic charge to the capacitor poly electrodes (1st poly Si) during the ion-implantation and reactive ion etching broke the 3 nm gate oxide of the 1st poly Si capacitor, causing bit errors of DRAM. This phenomena were published at the late news of ECS for the first time in the world in 1982 (1). Introduction of RTN gate oxide to prevent the boron penetration In early 1990’s CMOS technology changed from that of single n+-poly Si gate to dual poly Si gate (n+-poly Si for NMOSFETs and p+-poly Si for PMOSFETs) technology, in order to suppress the short-channel effect of PMOSFETs. Because the boron diffusion through the gate SiO2 during the high temperature thermal process is very large, the high-concentration boron penetration from the p+-poly Si to the PMOSFET channel through the gate SiO2 became a big problem. This was known to be solved by introduction of nitrogen to the SiO2. The author and his colleagues demonstrated that the RTN (Rapid Thermally Nitrided) SiO2 gate film completely suppress the boron penetration even the nitrogen concentration in SiO2 is only several percent, for the first time in 1990 (2). Introduction of direct-tunneling gate oxide for CMOS logic device It has been assumed that the gate oxide thinning limit would be 3 nm, because of the significant increase of the gate leakage current by direct-tunneling mechanism. However, the author and his colleagues demonstrated that MOSFETs with 1.5 nm thick direct-tunneling gate oxide operate quite normally, even though there is the direct-tunneling leakage, when decreasing the gate length less than 0.1 um, because the ratio between the gate leakage current and the drain current deceases in proportion to the square of the gate length reduction rate (3). Demonstration of the 0.4 nm EOT La-silicate gate oxide MOSFETs In order to decrease the gate length of MOSFETs to 5 nm, EOT (Equivalent Oxide Thickness) of the gate oxide should be 0.4 nm. The author and his colleagues developed La-silicate high-k metal gate technology and demonstrated the excellent operation of 0.4 nm EOT MOSFETs (4). Reference S. Sawada, S. Maeda, Y. Matsumoto, H. Iwai, H. Nihira, and O. Ozawa, “Degradation of thin gate oxide under process induced electrical stress”, 162nd ECS Fall Meeting, Recent Newspapers, Detroit, USA, October, (1982).T. Morimoto, H. S. Momose, K. Yamabe, and H. Iwai, “Prevention of boron penetration from p+ poly gate by RTP produced thin gate oxide”, ESSDERC 90, Nottingham, England, September, (1990), 73.H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, H. Iwai, “Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs”, in IEDM Tech. Dig., December, (1994), 593H. Iwai, T. Yasuda et al., “Research and development for second generation of ultra-thin gate insulator material”, NEDO Forum 2012 on energy saving technology, Tokyo, November, (2012): in Japanese

Enhanced Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor in the presence of interface traps

Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor (IGBT) is investigated during a gate voltage turn-on under the presence of interface carrier traps at the MOSFET gate oxide. The plateau, which is observed in the device gate-emitter voltage, increased with respect to both height and length. The plateau height is mainly determined by the density increase of trap states, which also causes slow charging of the gate capacitance in the overlap region that results in a longer plateau length. The shallow trap states contribute mainly to the plateau increase. It is observed that the switching loss at turn-on can increase by more than 60% due mainly to the carrier traps at the shallow trap states.

Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs

One of the most serious technology roadblocks for SiC DMOSFETs is the significant occurrence of early failures in time-dependent-dielectric-breakdown testing. Conventional screening methods have proved ineffective, because the remaining population is still plagued with poor reliability. The traditional local thinning model for extrinsic (early) failures, which guides the screening through burn-in measures, simply does not work. The fact that improved cleanliness control in the fabrication process does little to reduce early failures also suggests that local thinning due to contamination is not the root cause. In this paper, we propose a new lucky defect model where bulk defects in the gate oxide, introduced during growth, are responsible for the early failures. We argue that a local increase in leakage current via trap-assisted tunneling leads to early oxide breakdown. This argument is supported with oxide breakdown observations in SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> DMOSFETs, as well as simulations that examine various defect distributions and their impact on the resultant early failure distributions.