Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs

Abstract

One of the most serious technology roadblocks for SiC DMOSFETs is the significant occurrence of early failures in time-dependent-dielectric-breakdown testing. Conventional screening methods have proved ineffective, because the remaining population is still plagued with poor reliability. The traditional local thinning model for extrinsic (early) failures, which guides the screening through burn-in measures, simply does not work. The fact that improved cleanliness control in the fabrication process does little to reduce early failures also suggests that local thinning due to contamination is not the root cause. In this paper, we propose a new lucky defect model where bulk defects in the gate oxide, introduced during growth, are responsible for the early failures. We argue that a local increase in leakage current via trap-assisted tunneling leads to early oxide breakdown. This argument is supported with oxide breakdown observations in SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> DMOSFETs, as well as simulations that examine various defect distributions and their impact on the resultant early failure distributions.