Gate Oxide Process Research Articles

Total ionizing dose effects of 60Co-γ ray radiation on SiC MOSFETs with different gate oxide thickness

The application of SiC power devices in the space radiation environment not only requires good resistance to Single Event Effect (SEE) but also requires certain resistance to Total Ionizing Dose (TID) and long-term reliability. Increasing the thickness of the gate oxide layer (tox) can effectively improve the ability of SiC VDMOS to resist SEE. However, it will mainly impact its resistance to TID and Gate Oxide Integrity (GOI). Therefore, this paper compares the influence of tox on the radiation resistance and long-term reliability of SiC VDMOS under the same process and irradiation conditions. The experimental results show that after being irradiated by Cobalt-60 γ-rays, the static parameters of SiC VDMOS devices degrade severely with the increase of the tox; at the same time, the thick gate oxide process will also cause more defects in the gate oxide, leading to the decrease of the gate oxide long-term reliability, but it can be significantly improved after high temperature (HT) accelerated annealing. The research results suggest that the method of increasing tox should take into account the requirements of TID resistance and long-term reliability when improving the SEE radiation resistance of SiC VDMOS. This study is based on the improvement of electrical parameters and the analysis of reliability degradation of SiC VDMOS, providing experimental data support for determining the balance point of tox.

The Influence of Extended Defects in 4H-SiC Epitaxial Layers on Gate Oxide Performance and Reliability

For the ongoing commercialization of power devices based on 4H-SiC, increasing the yield and improving the reliability of these devices is becoming more and more important. In this investigation, gate oxide on 4H-SiC was examined by time-zero dielectric breakdown (TZDB) and constant current stress (CCS) time-dependent dielectric breakdown (TDDB) method in order to get insights into the influence of the epitaxial defects on the gate oxide performance and reliability. For that purpose, MOS capacitors with different gate oxides have been fabricated. Crystal defects in the epitaxial layers have been detected and mapped by ultraviolet photoluminescence (UVPL) and interference contrast (DIC) imaging. The results of the comparison of electrical data and surface mapping data indicate a negative influence on the leakage current behavior for some extended epitaxial defects. Results from TDDB measurement indicated numerous extrinsic defects, which can be traced back to gate oxide processing conditions and defect densities.

High Efficiency Over 70% at 3.6-GHz InAlN/GaN HEMT Fabricated by Gate Recess and Oxidation Process for Low-Voltage RF Applications

In this work, high-efficiency InAlN/GaN high electron mobility transistor (HEMT) is fabricated by recess and oxidation process under the gate (RAO) for low-voltage RF applications. Compared with conventional HEMT fabricated on the same heterojunction, RAO-HEMT exhibits a significant decrease in gate leakage, attributed to the thin oxide layer formed around and under the gate as well as adjustment of the location of the peak electric field and confinement of the strong electric field in the oxide. Due to the alleviated electric field as well as adoption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{N}_{{2}}\text{O}$ </tex-math></inline-formula> for plasma treatment, suppressed RF dispersion including the extremely low current collapse and negligible knee voltage walkout is obtained for RAO-HEMT. Although RAO-HEMT delivers lower saturation current as the result of the partial oxidation of the barrier under the gate, it shows a similar ON-resistance to conventional HEMT, which contributes to the reduction in knee voltage. Besides, higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{T}/{f}_{\text {MAX}}$ </tex-math></inline-formula> is achieved for RAO-HEMT, as the result of the higher dc transconductance and suppressed RF transconductance collapse as well as larger output resistance. Eventually, benefiting from the improvement in gate leakage, RF dispersion, knee voltage, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{\text {MAX}}$ </tex-math></inline-formula> by RAO, RAO-HEMT delivers both higher power-added-efficiency (PAE) and output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {OUT}}$ </tex-math></inline-formula> ) than conventional HEMT. At 3.6 GHz, RAO-HEMT provides a high PAE of 71% (74%) at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {DS}}}$ </tex-math></inline-formula> of 6 V (9 V), which performs better than most of the existing Si, GaAs, or GaN RF devices in PAE, revealing the great potential of InAlN/GaN RAO-HEMT in low-voltage low-power consumption RF applications.

Power Efficiency Characterization with Various Gate Oxide Thicknesses in Class DE Amplifiers for HIFU Applications

Skin and cancer cell treatments using high-intensity focused ultrasound (HIFU) have garnered considerable attention as a technology with fewer side effects. Hence, various schemes have been developed to operate ultrasound transducers with high efficiencies. Class DE power amplifiers operate in zero-voltage switching (ZVS) and zero-derivative switching (ZDS); therefore, high-efficiency operation is possible. However, during the CMOS process, a difference in efficiency arises depending on the gate oxide process, which has not yet been analyzed. In high-power devices, a thick oxide layer is primarily used to prevent breakdown. However, this can lead to a decrease in power efficiency. This study analyzes the overall power consumption for each oxide layer thickness during the AMS H35 CMOS process and compares its efficiency. The results confirm that an output power of approximately 1.8 W and a power efficiency of 94% can be obtained with just a relatively thin gate oxide thickness of approximately 10 nm. Furthermore, an additional power efficiency of approximately 3% can be obtained by reducing only the gate oxide thickness.

Improving the reliability of MOS capacitor on 4H-SiC (0001) with phosphorus diffused polysilicon gate

The interface states and reliability of 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) with thermal gate oxides have been researched widely. Several reports have researched the gate oxide process itself, but the effects of subsequent processes should not be ignored. In this paper, the reliability of thermal gate oxide films followed by polysilicon gate (poly-gate) process, which are widely used in MOSFET manufacture, and Al gates were compared. The poly-gate samples markedly affected the performance measured by time-zero dielectric breakdown and time-dependent dielectric breakdown methods because the phosphorus content diffused during poly-gate formatting; this was especially advantageous in reducing leakage current and improving the charge-to-breakdown (Q BD). After electronic characteristics measurements, scanning electron microscopy cross-sections were also used to analyze the breakdown mechanism. We observed an intermediate layer between the Al gate and the oxide that may cause the barrier height to be smaller than that of the poly-gate. The Al work function and polysilicon Fermi level determine the gate leakage currents and the resultant gate oxide reliability, whereas the Al2O3 gate sample has a smaller work function offset (0.7 eV) than ideal Al gate and poly-gate samples. The results imply that the reliability of the Al gate samples may be an intrinsic problem.

Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultrahigh Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimization to minimize the gate leakage current towards low-power MCU applications. Based on the 55 nm node, it has been found both theoretically and experimentally that the leakage level has been significantly reduced at different temperature in n-FET, p-FET, data flip-flop (DFF) and inverter (INV). Upon MCU testing under active, sleep and deep sleep modes, obvious decrease in the power consumption is also achieved, providing a promising optimization approach towards a better balance between the speed and power in modern MCU technology.

Microwave plasma oxidation kinetics of SiC based on fast oxygen exchange

Gate oxide process is one of the most important issues for making high performance SiC power MOSFETs. Previously, it has been demonstrated that plasma oxidation provides a promising way for making advanced SiC power MOSFETs. To further boost the performance of SiC MOSFETs, understanding the plasma oxidation kinetics becomes inevitable. In this contribution, microwave plasma oxidation kinetics of SiC are investigated by labelling the SiO2 with 18O isotopes. Growth of SiO2 chemically comparable to that from 1300 °C thermal oxidation with flat interface is confirmed by XPS and TEM. Moreover, SiO2 with thickness over 50 nm is demonstrated to be obtainable with rapid growth rate (>2 nm/min) at relatively low temperatures (<1000 °C) by properly adjusting the power and pressure. During the plasma oxidation, fast oxygen exchange is proved by experiments, which is significantly different from the oxidation mechanism of thermal oxidation. Furthermore, several possible reasons, such as thermal effect, water vapor oxidation and atomic oxygen diffusion for the fast oxygen exchange are discussed and eliminated, while the presence of defects in SiO2 or SiO2 structural changes are left as possible reasons for the fast oxygen exchange.

Monitoring on Creation and Annihilation of Interface Trap Levels with NO Oxidation, Re-Oxidation and N&lt;sub&gt;2&lt;/sub&gt; Annealing with Conductance Measurements

We have determined, using the Conductance-Frequency (G-ω) Technique, the creation and annihilation process of the 3 interface trap levels (OX, OX’ and NI levels) previously reported [1-3] and their possible correlation to inversion electron trapping and mobilities. The measurements were carried out on various 4H-SiC Metal Oxide Semiconductor (MOS) capacitors that have been processed using several gate oxide processes [2,5,6]. Our analysis focus on the correlation of the interface trap levels on the process conditions so as to first understand and then control their formation.

A PNP-triggered dynamic substrate GGNMOS with improved performances

A novel PNP-triggered dynamic substrate GGNMOS (gate-grounded NMOS) structure is proposed and verified in 0.18 μm salicided CMOS process. Owing to the dynamic substrate technique and imbedded PNP transistor which injects triggering current to the substrate under ESD (electrostatic discharge) events, the proposed structure features a small trigger voltage, a small snapback region, a high robustness, and a larger margin of ESD design window is achieved. Compared with traditional dynamic substrate GGNMOS, the proposed structure promotes FOM (figure of merit) by 60%. So it is a more feasible solution in ESD protections applications of low-voltage and thin gate oxide process for its overall improved performances.

Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O) devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are investigated. The I/O device degrades more than the Core device under the same stress electric field due to the different gate oxide processes in these two types of devices. Both the oxide trap charge and interface trap lead to the transfer characteristics degradations of the device after NBTI. While the near interfacial traps result in the increase of low frequency noise (LFN). The trap densities near the silicon/gate oxide interface introduced by stress are extracted using the LFN method. NBTI-induced gate current increase is observed for Core device, but not for I/O device. It is result from the enhanced tunneling process, which is induced by the increase of electric field in the gate oxide after charge trapping at or near the channel interface. The gate width and length dependences of NBTI are observed. The enhanced NBTI degradation observed in short channel and narrow channel device is result from the enhanced NBTI effect at channel edge regions. The larger hole concentration is a main cause of the more serious NBTI degradation at the channel edge regions, including the nearby region of STI sidewall along the channel width direction and the gate edge region along the channel length direction. This conclusion is also verified by the TCAD simulations.

1200 V SiC MOSFETs with Stable V&lt;sub&gt;TH&lt;/sub&gt; under High Temperature Gate Bias Stress

In this work, threshold voltage drift of SiC MOSFET devices have been investigated. The drift during positive gate bias application was found to be moderate for three commercial grade devices, while the results for negative gate bias application differ widely. We demonstrate ON Semiconductor SiC MOSFETs with threshold voltage stability under both positive and negative bias stress due to an improved gate oxide process, and the influence of high field stress on the threshold voltage is additionally discussed. A long term transient high temperature gate bias stress is shown to cause a slight positive shift in the threshold voltage of the ON Semiconductor devices, while the on resistance remains constant.

Improved channel mobility of 4H-SiC n-MOSFETs by ultrahigh-temperature gate oxidation with low-oxygen partial-pressure cooling

An n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) with high field-effect mobility (μFE) on 4H-SiC (0001) was fabricated using an ultrahigh-temperature gate-oxidation technique, and its improved channel mobility was demonstrated by employing a low-oxygen partial-pressure cooling procedure. The ideal flatband voltage for n-MOS and p-MOS capacitors and hysteresis-free drain current–gate voltage (Id–Vg) characteristics were obtained through gate oxidation at 1450 °C in 100% O2 ambient at 1 atm followed by the low-oxygen partial-pressure (1%) rapid-cooling procedure. From the Id–Vg characteristics, a μFE of 15.8 cm2 V−1 s−1 was obtained under the pure O2 gate-oxidation process.

Punch-Through Stop Doping Profile Control via Interstitial Trapping by Oxygen-Insertion Silicon Channel

Interstitial trapping by oxygen-inserted silicon channel results in blocking of boron and phosphorus transient enhanced diffusion as well as retention of channel boron profiles during the gate oxidation process. The enhanced doping profile control capability is applicable to punch-through stop of advanced CMOS devices and its benefits to 28nm planar CMOS and 20nm bulk FinFET devices projected by TCAD have been discussed.

Designing 4H-SiC P-shielding trench gate MOSFET to optimize on-off electrical characteristics

In order to enhance specific on-resistance (Ron,sp), the trench gate structure was also introduced into 4H-SiC MOSFET as Si MOSFET. But the 4H-SiC trench gate has worse off-state characteristics than the Si trench gate due to the incomplete gate oxidation process (Šimonka et al., 2017). In order to overcome this problem, P-shielding trench gate MOSFET (TMOS) was proposed and researched in previous studies. But P-shielding has to be designed with minimum design rule in order to protect gate oxide effectively. P-shielding TMOS also has the drawback of on-state characteristics degradation corresponding to off state improvement for minimum design rule. Therefore optimized design is needed to satisfy both on and off characteristics.In this paper, the design parameters were analyzed and optimized so that the 4H-SiC P-shielding TMOS satisfies both on and off characteristics. Design limitations were proposed such that P-shielding is able to defend the gate oxide.The P-shielding layer should have the proper junction depth and concentration to defend the electric field to gate oxide during the off-state. However, overmuch P-shielding junction depth disturbs the on-state current flow, a problem which can be solved by increasing the trench depth. As trench depth increases, however, the breakdown voltage decreases. Therefore, trench depth should be designed with due consideration for on-off characteristics. For this, design conditions and modeling were proposed which allow P-shielding to operate without degradation of on-state characteristics.Based on this proposed model, the 1200 V 4H-SiC P-shielding trench gate MOSFET was designed and optimized.

Dynamic Characterization of the Threshold Voltage Instability under the Pulsed Gate Bias Stress in 4H-SiC MOSFET

The threshold voltage (Vth) instability of 4H-SiC MOSFETs was investigated using high-speed IV measurement instrument. DC stress measurement of wide time span ranging from 10-6 to 103 s without relaxation effect was conducted. The high-speed measurement allowed of dynamic ΔVth measurement under pulsed AC gate bias stress. We investigated effects of NO POA in gate oxidation process on the Vth instabilities.

Thermal Budget Reduction in Triple Gate Oxide Process by Wet Etch Technique

As transistor geometry shrunk and System on Chip (SoC) requirement increased, chips with multiple operation voltages become regular criteria in IC design specification. It means multiple gate oxide thicknesses have to be integrated in semiconductor manufacturing front-end-of-line (FEOL) process. However, process thermal budget will be one of the concerns of transistor electrical performance shift resulted from diffusion of implantation species. In this study, thicker gate oxide (MV) was etched back by wet chemical as thinner gate oxide (I/O) to reduce gate oxide formation thermal budget. However, wet etching rate was degraded after clean and lithograph sequential processes. The oxidant, in wet clean chemical, oxidized silicon dioxide surface Si-H bonding into Si-OH which reacted with Hexamethyldisilazane (HMDS), commonly used as lithography adhesion material, and form an extremely thin Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on gate oxide surface. Fortunately, Trimethylsiloxy monolayer consists of Si-O bonding and Trimethylsilyl group (-Si(CH3)3) and can be easily removed by O2 plasma treatment.

Thermal Budget Reduction in Triple Gate Oxide Process by Wet Etch Technique

As transistor geometry shrunk and System on Chip (SoC) requirement increased, chips with multiple operation voltages become regular criteria in IC design specification. It means multiple gate oxide thicknesses have to be integrated in semiconductor manufacturing front-end-of-line (FEOL) process. However, process thermal budget will be one of the concerns of transistor electrical performance shift resulted from diffusion of implantation species. In this study, thicker gate oxide (MV) was etched back by wet chemical as thinner gate oxide (I/O) to reduce gate oxide formation thermal budget. However, wet etching rate was degraded after clean and lithograph sequential processes. The oxidant, in wet clean chemical, oxidized silicon dioxide surface Si-H bonding into Si-OH which reacted with Hexamethyldisilazane (HMDS), commonly used as lithography adhesion material, and form an extremely thin Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on gate oxide surface. Fortunately, Trimethylsiloxy monolayer consists of Si-O bonding and Trimethylsilyl group (-Si(CH3)3) and can be easily removed by O2 plasma treatment. To reduce thermal budget, induced from furnace process of gate oxide formation, in triple gate oxide process, I/O gate oxide was obtained by thicker MV gate oxide wet chemical etching back, showed as Figure 1. However, when I/O gate oxide was removed at LV area, showed as Figure 1, step 6, wet etching rate was decreased. Reviewing similar process in I/O area wet etching back process, showed as Figure 1, step 4, the wet etching rate was normal. To figure out why wet etching rate is different between step 4 and step 6 in Figure 1, both 1:200 dilute HF and gas type HF etching rate and etching rate variation percentage with as growth data were collected by blanket silicon dioxide (SiO2) wafer which quality is same as MV gate oxide and result is showed as Table I. Clean is Piranha and SC1, including SPM (sulfuric acid and hydrogen peroxide mixture, H2SO4+ H2O2) and APM (ammonia, hydrogen peroxide and deionized water mixture, NH3+ H2O2+ H2O) process steps. In Table I, 1:200 dilute HF etching rates are normal after clean and after HMDS treatment, respectively. However, once combining clean and HMDS treatment, 1:200 dilute HF etching rate was decreased around 7.2%, but gas type HF etching rate didn’t show the same phenomena. Moreover, additional O2 plasma treatment was added in final step, 1:200 dilute HF etching rate became normal. HMDS is commonly used adhesives between photo resist and coating surface. The mechanism is silylation reaction, showed as Figure 2. HMDS reacted with SiO2 surface hydroxyl group (-OH) and formed Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on SiO2 surface which changing surface property from hydrophilic into hydrophobic. Adhesion between Photo resist and SiO2 surface had been improvement due to the enhancement of van der Waals’ force. Trimethylsiloxy monolayer (Si-O-Si(CH3)3) formation amount depends on hydroxyl group (-OH) amount on SiO2 surface. From Table II, after clean process, SiO2 surface hydroxyl group (-OH) increase due to the existence of hydrogen peroxide in clean chemical. The SiO2 surface become more hydrophilic, water contact angle decreased from 35.3° to 14.8°. After HMDS priming, SiO2 surface hydroxyl group (-OH) were substituted by Trimethylsiloxy group (-O-Si(CH3)3). The SiO2 surface become hydrophobic, water contact angle increased from 35.3° to 52.2°. After combining clean and HMDS processes, the water contact still increased from 52.2° to 59.1°. It means after clean process, some Si-H bondings oxidized by hydroperoxide into hydroxyl group (-OH), which will increase final Trimethylsiloxy monolayer (Si-O-Si(CH3)3) amount on SiO2 surface. After O2 plasma process, SiO2 surface was back to as growth condition by compatible water contact angle result. Reviewing Table I data, 1:200 dilute HF etching rate dropped main root cause is the existence of Trimethylsiloxy monolayer (Si-O-Si(CH3)3). The densification of this monolayer might be not as good as from deposition process and results in gas type HF can easily penetrate to bottom oxide layer and no etching rate was impacted. Fortunately, Trimethylsiloxy monolayer (Si-O-Si(CH3)3) can be removed by O2 plasma treatment. To replace one of triple gate oxide growth under high temperature by thicker gate oxide wet etching back process. Post etched clean step and HMDS in following step will interfere with dilute HF etching behavior due to Trimethylsiloxy monolayer (Si-O-Si(CH3)3) formation. By adding additional O2 plasma treatment, Trimethylsiloxy monolayer (Si-O-Si(CH3)3) can be easily and successfully removed and wet dilute HF SiO2 etching rate was back to normal. The thermal budget of triple gate oxide process can be successfully reduced by gate oxide wet etching back technique. Figure 1

Practical applications of SiC-MOSFETs and further developments

The next generation power modules using SiC-MOSFETs have been developed for over ten years. From our successful results, we have released SiC power modules which have been used in railway vehicles, industrial machines and home appliances, etc. Low on-resistance 3.3 kV SiC-MOSFETs have been realized by JFET doping and they demonstrated a loss reduction of 55% in a traction inverter compared to a conventional system. In the case of a 1.2 kV MOSFET, a 1 cm2 die verified that it can control a large current of over 600 A. For home appliances, we reduce the trade-off between the threshold voltage and channel mobility by a new gate oxide process. High threshold voltage SiC-MOSFETs having a low on-resistance contribute to the low cost installation of SiC-MOSFETs into air conditioners and achieved a loss reduction of 45% in DC converters. For further reduction of conduction loss, we investigated new structures and technologies. Trench SiC-MOSFETs having a bottom p-well verify lower on-resistance and a larger SCSOA than those of planar MOSFETs. The optimization of the dopant concentration in the drift layer and a reduction of wafer thickness verified the reduction of on-resistance. They are expected to contribute to a lower power loss.

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.

Comparative Study of Characteristics of Lateral MOSFETs Fabricated on 4H-SiC (11-20) and (1-100) Faces

We have fabricated the lateral MOSFETs on (11-20) and (1-100) faces and have compared the properties between these faces with various gate oxide processes. It has been demonstrated that (11-20) and (1-100) faces show comparable electrical properties with nitridation treatment on the gate oxide. Our result indicates that both faces exhibit the similar trend of the mobility vs. Dit. Furthermore, it has been shown that NO POA is beneficial to both faces in achieving high channel mobility and suppressed Vt instability.