Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

Zijian Zhao,Yao Zhou,Hao Zhu,Qingqing Sun,David Wei Zhang

doi:10.1109/jeds.2021.3123978

Zijian Zhao, Yao Zhou + Show 3 more

Open Access

https://doi.org/10.1109/jeds.2021.3123978

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Abstract

The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultrahigh Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimization to minimize the gate leakage current towards low-power MCU applications. Based on the 55 nm node, it has been found both theoretically and experimentally that the leakage level has been significantly reduced at different temperature in n-FET, p-FET, data flip-flop (DFF) and inverter (INV). Upon MCU testing under active, sleep and deep sleep modes, obvious decrease in the power consumption is also achieved, providing a promising optimization approach towards a better balance between the speed and power in modern MCU technology.

Highlights

With the emerging technologies in internet-of-things (IOT) and artificial intelligence, there is a growing demand for the high-performance microcontroller unit (MCU), which integrates central processing unit (CPU), memory, digital, analog, input/output and other components for signal and data processing
We studied the electrical performance of the ultrahigh Vth (UHVT) devices by optimizing tox and doping concentration, and compared it to the performance of the standard high Vth (HVT) device
We have studied the optimization techniques to lower the power consumption in UHVT FET devices focusing on the gate oxide thickness and Vth implantation process

Summary

Introduction

With the emerging technologies in internet-of-things (IOT) and artificial intelligence, there is a growing demand for the high-performance microcontroller unit (MCU), which integrates central processing unit (CPU), memory, digital, analog, input/output and other components for signal and data processing. We propose and study the process and device engineering to improve the gate leakage in UHVT devices while maintaining a stable Vth level through gate oxide thickness and LDD doping concentration co-optimization. Both simulated and experimental work have confirmed the reduced leakage current in n-type and p-type devices. Practical MCU testing further confirms the improvement in system performance under various operation modes upon the optimization method

EXPERIMENTAL DETAILS

RESULTS AND DISCUSSION

CONCLUSION