Metal Gate Work Function Research Articles

The impact of high-frequency characteristics induced by intrinsic parameter fluctuations in nano-MOSFET device and circuit

This work estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal–oxide–semiconductor field effect transistors (MOSFETs) and circuits by using an experimentally validated three-dimensional device and coupled device–circuit simulations. The dominance fluctuation source in threshold voltage, gate capacitance, cut-off frequency, high-frequency gain, 3 dB bandwidth, unity-gain bandwidth, power, and the power-added efficiency has been found. Similar to the trend of the cut-off frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario.

Tunneling of holes observed at work function measurements of metal/HfO2/SiO2/n-Si gate stacks

The voltage bias that causes a transition from direct tunneling to Fowler–Nordheim tunneling in the current-voltage characteristic of a metal/HfO2/SiO2/n-Si capacitor was measured. The transition occurs in the negative gate voltage regime and can be attributed to conduction of electrons from the metal through a defect level in the HfO2 or to conduction of holes from the Si through the valence band of the HfO2. The dependence of the determined barrier height on the gate-metal work function indicates the validity of the latter model.

Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High-$k$/Metal Gates CMOS FinFETs for Multi- $V_{\rm Th}$ Engineering

Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Th</sub> ) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Th</sub> , low T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> (~1.4 nm), and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> (~780 ¿A/¿m) for N/PMOS without any intentional strain enhancement.

Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies

This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) ; however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and is therefore proportional to the trend of ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> . The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.

Impact of Oxygen on Work Function of Ru Oxide Metal Gate

A mechanism of effective work function change of the Ru oxide metal gate under various anneal conditions has been studied. High temperature annealing was found to result in changing the tetragonal phase of RuO 2 to the hexagonal phase characteristic for Ru metal. By extracting the electrode-dielectric band offset magnitude, it was confirmed that such a change in the stoichiometry of Ru oxide leads to the lower effective work function values of the postanneal Ru oxide/high-k gate stacks. The low temperature oxygen anneal treatment of the high temperature annealed Ru oxide electrode stacks recovers the high work function value by supplying oxygen into the decomposed Ru oxide.

Oxygen incorporation in TiN for metal gate work function tuning with a replacement gate integration approach

In this study, we used oxygen to increase the work function of a TiN gated stack. To prevent the EOT growth associated with oxygen incorporation, we proposed a novel replacement gate flow, where oxygen incorporation by O 2 anneal on a thin TiN layer was performed after dopant activation. With this novel flow, a maximum work function tuning range of ∼0.32 eV was achieved without significant EOT penalty, making it attractive for p-type metal gate integration.

A New Two-Dimensional Analytical Model for Nanoscale Symmetrical Tri-Material Gate Stack Double Gate Metal–Oxide–Semiconductor Field Effect Transistors

Based on the resultant solution of two-dimensional (2D) Poisson's equation in silicon region, a new, compact and analytical model for nanoscale fully depleted, symmetrical tri-material gate stack double-gate (STMGSDG) metal–oxide–semiconductor field-effect transistor (MOSFET) has been developed. The STMGSDG MOSFET exhibits significantly reduced short-channel effects (SCEs) when compared with the symmetrical single-material gate stack double-gate (SSMGSDG) MOSFET. It is found that the threshold voltage roll-off for the fully depleted STMGSDG MOSFET can be effectively reduced by using both thin Si film and thin gate oxide. Besides, the high ratio of large work function of metal gate 1 (L1) to the total gate can efficiently suppress the drain-induced barrier lowering (DIBL) and maintain the low threshold voltage degradation. This study not only presents a precise 2D analytical model of the surface potential and threshold voltage, but also discusses the electric field distribution in the channel region, subthreshold swing and subthreshold current for the STMGSDG MOSFET. The new model is verified to be in a good agreement with numerical simulation results over a wide range of the device parameters.

High Depth Resolution Depth Profile Analysis of Ultra Thin High-κ Hf Based Films using MEIS Compared with XTEM, XRF, SE and XPS

Nanometre thin high-k hafnium oxide (HfO2) layers combined with a sub-nm SiO2 layers or Hf silicate have become Si compatible gate dielectrics. Medium energy ion scattering (MEIS) analysis has been applied to a range of such MOCVD grown HfO2/SiO2 and HfSiOx(60%Hf)/SiO2 gate oxide films of thickness between 1 and 2 nm on top of Si(100), before and after decoupled plasma nitridation (DPN). MEIS in combination with energy spectrum simulation provides quantitative layer information with sub-nm resolution on these layer structures and their atomic composition that is in excellent agreement with a) the as grown layer parameters and b) results obtained from techniques, such as SE, XPS, XRF and XTEM. MEIS analysis of a metal gate, high-k TiN/Al2O3/HfO2/SiO2/Si stack shows the interdiffusion, after thermal treatment, of Hf and Al from the caplayer, which was inserted to modify the metal gate work function.

TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation

Part I of this paper dealt with the hot carrier reliability evaluation of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET involving channel recession and gate electrode workfunction engineering integration onto the conventional MOSFET, using an ATLAS device simulator. It was demonstrated that with the gate stack architecture incorporated onto the GEWE-RC MOSFET and tuning of various structural design parameters such as gate length ( L G ), negative junction depth (NJD), substrate doping ( N A ), gate metal workfunction, substrate bias ( V S U B ), drain bias ( V D S ) and gate oxide permittivity ( ε o x 2 ), excellent hot carrier immunity can be achieved in terms of conduction band offset, reduced electron velocity, electron temperature, hot electron injected gate current and impact ionization substrate current. This paper focuses on the analog and large signal performance metrics in terms of linearity, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters. Moreover, the paper also discusses the effect of gate stack architecture and various design parameters such as L G , NJD, N A , gate metal workfunction and ε o x 2 for different substrate ( V S U B ) and drain to source ( V D S ) voltages. The work, thus, proves the effectiveness of GEWE-RC for RFICs with a higher efficiency, better linearity performance; and designing and modeling of power amplifiers.

Effects of surface alloying and orientation on work function of MoTa metal gate

Work functions of sub- and monolayers Mo on metal Ta of various orientations are investigated using first-principles methods based on density functional theory. The calculated results reveal that the work function has strongly orientation dependence. However, for a given surface orientation, the work function is insensitive to distributions of Ta/Mo atoms in the surface layer. Moreover, it is found that work functions of the (100) and (111) surfaces increase with increasing Mo composition in the surface layer but those of the (110) decrease. By analysis of surface dipole density, it is found that the metal work function is mainly determined by surface orientation and surface charge redistribution.

Channel length scaling and the impact of metal gate work function on the performance of double gate-metal oxide semiconductor field-effect transistors

In this paper, we study the effects of short channel on double gate MOSFETs. We evaluate the variation of the threshold voltage, the subthreshold slope, the leakage current and the drain-induced barrier lowering when channel length LCH decreases. Furthermore, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson-Schrodinger solver in two dimensions over the entire device. A good agreement with numerical simulation results is obtained.

Work Function Engineering Within a Single Metal Gate Stack: Manipulating Terbium- and Aluminum-Induced Interface Dipoles of Opposing Polarity

In this paper, a systematic study on combining n-type and p-type interface dipoles for metal gate work function (Phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) engineering within the same gate stack was conducted. Ultrathin terbium (Tb) and aluminum (Al)-based interlayers (ILs) were utilized for n- and p-type dipole formation, respectively, to modulate the net interface dipole magnitude and polarity within a metal gate stack. By controlling the net interface dipole through Tb- and Al-based ILs, continuous TaN Phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> tunability of ~ 0.7-0.8 eV (after either a 500degC or 950degC anneal) on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric was attained. The reversal of net interface dipole polarity was demonstrated using both TaN/SiO2 and TaN/high-kappa gate stacks by varying IL metal species and anneal conditions. A convenient way in reversing a Tb-induced (n-type) dipole through Al-incorporation via the TaN metal gate using a ldquogate-firstrdquo process is also shown. The dominant dipole that results in the metal gate stack hinges critically on the reactions of Al and Tb with SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (or underlying SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> for high-kappa stacks) for Al-O-(Si) and Tb-O-Si bond formation, respectively. This concept of manipulating interface dipoles of opposing polarity for metal gate Phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> tunability could open up new avenues for achieving multiple Phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> using a single metal gate and a simple integration scheme.

Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO 2 film

We have investigated the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with Er metal gate on SiO 2 film. Rapid thermal annealing (RTA) process leads to the formation of a high- k Er-silicate gate dielectric. The in situ high-voltage electron microscopy (HVEM) results show that thermally driven Er diffusion is responsible for the decrease in equivalent oxide thickness (EOT) with an increase in annealing temperature. The effective work function ( Φ m,eff) of Er metal gate, extracted from the relations of EOT versus flat-band voltage ( V FB), is calculated to be ∼2.86 eV.

Crucial integration of high work-function metal gate and high-k blocking oxide on charge-trapping type flash memory device

Charge-trapping type flash memory devices with various integrations of metal gates having different work functions and blocking oxides were investigated in this work. Improved erasing speed together with acceptable reliability characteristics can be achieved by the integration of high work-function metal gate and high-k blocking oxide due to an efficient suppression of electron back tunneling through the blocking oxide during erasing operation for the MoN sample. Specifically, the high work-function value of MoN metal gate can be kept only by integrating with the Al2O3 blocking oxide because it can suppress the formation of molybdenum-silicide. Moreover, high-speed erasing can also be demonstrated by combining the MoN metal gate with an HfAlO charge trapping layer when band-to-band hot hole erasing method is adopted.

TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture&amp;#x2014;Part I: Hot-Carrier-Reliability Evaluation

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NA</i> ), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.

Disorder and surface effects on work function of Ni-Pt metal gates

Work functions of NiPt alloys with different compositions are investigated using first-principles methods based on density-functional theory. Results of our calculations reveal that surface alloy composition has a significant effect on the work function of the NiPt alloy. However, for a given surface composition, the work function is insensitive to the distributions of Ni/Pt atoms in the alloy and it is only slightly affected by alloy disorder. Our work suggests surface atomic modification as a promising way of tuning the work function of alloy metal gate.

In0.53Ga0.47As based metal oxide semiconductor capacitors with atomic layer deposition ZrO2 gate oxide demonstrating low gate leakage current and equivalent oxide thickness less than 1nm

The paper demonstrates properties of metal oxide semiconductor capacitors fabricated on molecular beam epitaxial In0.53Ga0.47As wafers with the atomic layer deposition ZrO2 gate oxide. The equivalent oxide thickness of 0.8nm was obtained for 5nm thick ZrO2, while the gate leakage current density at VFB+1V was as low as 0.1A∕cm2. Sensitivity of capacitance-voltage characteristics to the metal gate work function along with low frequency dispersion of ∼5%/decade served as a strong evidence of a nonpinned Fermi level at the oxide-InGaAs interface. Both electrical and structural properties remain stable up to 800°C.

Cathode Electron Injection Breakdown Model and Time Dependent Dielectric Breakdown Lifetime Prediction in High-k/Metal Gate Stack p-Type Metal–Oxide–Silicon Field Effect Transistors

We have investigated the time dependent dielectric breakdown (TDDB) for a high-k/metal gate p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) under inversion stress. We have found that electrons, injected from the cathode, are minority carriers in the gate leakage current and play an important role in determining TDDB lifetime and that the existence of oxygen vacancies in HfSiON, decide the electron current mechanism in HfSiON. Since electrons from the cathode flow as a tunneling current with the effective barrier height determined by the energy level of the oxygen vacancies in the HfSiON, electron current is strongly dependent on the effective work function of the metal gate. That implies that a higher work function should be effective to suppress of electron current, due to the elevated barrier height for electrons. Therefore, the formation of a high work function metal gate is essential, not only for low threshold voltage of pMOSFETs but also to achieve long TDDB lifetimes.

Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

Uniaxial four-point wafer bending stress-altered gate tunneling currents are measured for germanium (Ge)/silicon (Si) channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with HfO2/SiO2 gate dielectrics and TiN/P+ poly Si electrodes. Carrier separation is used to measure electron and hole currents. The strain-altered hole tunneling current from the p-type inversion layer of Ge is measured to be ∼4 times larger than that for the Si channel MOSFET, since the larger strain-induced valence band-edge splitting in Ge results in more hole repopulation into a subband with a smaller out-of-plane effective mass and a lower tunneling barrier height. The strain-altered electron tunneling current from the metal gate is measured and shown to change due to strain altering the metal work function as quantified by flatband voltage shift measurements of Si MOS capacitors with TaN electrodes.

Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part I: Impact of Gate Metal Workfunction Engineering

In this paper, we present a simulation study, using ATLAS-2D, of analog circuit performance metrics for the dual-material gate (DMG) MOSFETs in Part I. Part II focuses on the impact of double-layer gate stack architecture on the analog performance and fT-gain relationship of the silicon-on-nothing MOSFETs with and without DMG. The simulation results in Part I demonstrate that, out of the several combinations in DMG MOSFET design studied, the DMG device with an LM1/L ratio of frac12 amalgamates the advantages of using a high metal workfunction gate M1 and a low metal workfunction gate M2 in the most efficient manner. An increase in early voltage and a reduced output conductance from the DMG MOSFET design are the driving forces for the observed performance improvement.