TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

Abstract

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NA</i> ), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.