Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High-$k$/Metal Gates CMOS FinFETs for Multi- $V_{\rm Th}$ Engineering

Abstract

Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Th</sub> ) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Th</sub> , low T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> (~1.4 nm), and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> (~780 ¿A/¿m) for N/PMOS without any intentional strain enhancement.