Metal Gate Work Function Research Articles

Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In0.53Ga0.47As GAA MOSFET

We investigate the impacts of random dopant (RD) and gate workfunction variability on the subthreshold characteristics of a 50-nm-gate-length inversion-mode gate-all-around In0.53Ga0.47As MOSFET using a 3-D finite-element quantum-corrected drift-diffusion device simulator calibrated to experimental data. We have studied threshold voltage, off-current, and subthreshold slope variations. The workfunction variations on the subthreshold characteristics dominate and decrease with the reduction in grain diameter. The simulated grain diameters of 10, 7, and 5 nm exhibit threshold voltage standard deviations of 52, 41, and 27 mV, respectively. These values are larger than those observed in TiN-metal-gate Si FinFETs for a similar gate length. The impact of RD fluctuations is negligible when compared with bulk Si MOSFETs, giving a threshold voltage spread of only 6 mV.

Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology

This paper investigates the threshold voltage sensitivity to metal gate work-function for n-channel double gate fin field-effect transistor (FinFET) structures and evaluates the short channel performance of the device using threshold voltage dependence on metal gate work-function analysis. We carried out the study for a double gate n-channel fin field-effect transistor (n-FinFET) with parameters as per the projection report of International Technology Roadmap for Semiconductors, ITRS-2011 for low standby power (LSTP) 20 nm gate length technology node. In the present study device simulation have been carried out using PADRE simulator from MuGFET, which is based on the drift-diffusion theory. Our results show the accuracy and validity of classical drift-diffusion simulation results for transistor structures with lateral dimensions 10nm and above. The subthreshold behavior of device improves with increased metal gate work-function. The results also show that a higher gate work-function (≥5 eV) can fulfill the tolerable off-current as projected in ITRS 2011 report. The SCE in FinFET can reasonably be controlled and improved by proper adjustment of the metal gate work-function. DIBL is reduced with the increase in gate work function.

A novel spin modulation of work function for C adsorbed Cr/Fe(001) metal gate

Work functions and magnetic moments of C adsorbed Cr/Fe(001) surfaces with different C coverages θ and magnetic alignments (parallel or antiparallel) between Cr and Fe atom moments are investigated using first-principles methods based on density functional theory. The calculated results reveal that the spin configuration plays a significant role in determining the work function of the systems. The work functions of the systems with parallel states are evidently larger than those with antiparallel states. Moreover, for θ≤0.5 ML, with increasing value of θ, the work function increases from 4.23 eV to 5.13 eV for antiparallel states and from 4.47 eV to 5.44 eV for parallel states. While for θ>0.5 ML, the work function decreases with increasing value of θ. It can be also found that, for θ≤0.5 ML, the smaller the Cr and Fe magnetic moments are, the lower the Fermi energy EF is and the larger the work functions of the systems are. Based on analysis and discussion, we conclude that the changes of the work functions and magnetic moments are mainly determined by those of Fermi level and density of state (DOS) induced by the spin polarization, the electron transfer and the surface structure. Our work strongly suggests that controlling the magnetic states is a promising way for modulating the work function of magnetic metal gate.

Effect of oxygen on tuning the TiNx metal gate work function on LaLuO3

This paper presents experimental evidence on effective work function tuning due to the presence of oxygen at the TiNx/LaLuO3 interface. Two complementary techniques, internal photoemission and X-ray photoelectron spectroscopy, show good agreement on the position of the metal gate Fermi level to conduction (2.79±0.25eV) and valence (2.65±0.08eV) band edge for TiNx/bulk LaLuO3 gate stacks. The chemical shifts of Ti2p and N1s core levels and different degree in ionicity of TiNx metal gates correlate with the observed valence band offset shifts. The results have significance for setting the band edge work function and resulting low threshold voltage for ultimately scaled LaLuO3-based p-metal oxide semiconductor field effect transistor devices.

Electrical and Reliability Characteristics of HfLaTiO-Gated Metal–Oxide–Semiconductor Capacitors With Various Ti Concentrations

Electrical and reliability characteristics of metal-oxide-semiconductor (MOS) capacitors with various-Ti-concentration-doped HfLaTiO/interfacial layer (IL)/P-Si(100) stacked structures are presented. Charge carrier generation/trapping and the related mechanisms of a thin HfLaTiO/IL stack in n-type MOS capacitors have been investigated under constant gate voltage stress. The mechanisms related to larger positive charge generation in the HfLaTiO gate dielectric bulk can be attributed to Ti-doped HfLaTiO dielectric. This is confirmed from the density of stress-induced oxide trapped charges. Moreover, more positive charges are induced in the HfLaTiO dielectric with increasing postdeposition annealing temperature. By developing proper Ti concentration in HfLaTiO dielectrics, the enhanced equivalent oxide thickness (EOT = ~ 0.5 nm) and the interface trap density ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) were demonstrated. Furthermore, the Ti-doped HfLaTiO dielectric is helpful for enhanced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -value of the HfLaTiO film (lower EOT), but the optical bandgap properties could be degraded. Energy band diagram of MOS capacitor with an HfLaTiO dielectric was achieved by the measurement of the effective work function of Ta metal gate deposited on HfLaTiO dielectric, the optical bandgaps of HfLaTiO dielectric, and Schottky barrier height (Φ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</i> ) at the Ta/HfLaTiO interface.

Thin Film Challenges in 28nm Technology Node

During 28nm technology node process development, a couple of dozens new thin films and advanced thin film processes have been introduced to meet needs of the CMOS circuit performance. These new films and processes are used for micro-patterning, gap-fill, high-k metal gate (HKMG) work function metals and electrodes, electrical and reliability performance, etc. This article shall report the latest progress in thin film developments at the leading Chinese semiconductor company, SMIC. Some key challenges in the areas mentioned above will be elaborated and various new thin film requirements will be discussed. Examples of some thin film process developments, especially in the micro-patterning, Metal Gate and STI and ILD gap-fill, and HKMG work function tuning, will be provided, and the preliminary results will be presented.

GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL. On the other hand, the impact of the gate dielectric on the GIDL for p- channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed.

AC analysis of nanoscale GME-TRC MOSFET for microwave and RF applications

In this paper, the RF performance for Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been investigated and the results so obtained are compared with Trapezoidal Recessed Channel (TRC) MOSFET and Rectangle Recessed Channel (RRC) MOSFET, using device simulators; ATLAS and DEVEDIT. Further, the impact of technology parameter variations in terms of negative junction depth (NJD), gate metal workfunction difference, substrate doping ( N A) and corner angle, on GME-TRC MOSFET has also been evaluated. The simulation study shows the increase in transconductance and decrease in parasitic capacitance, which further contributes towards a significant improvement in cut-off frequency ( f t) in GME-TRC MOSFET as compared to conventional TRC and RRC MOSFETs. Moreover, the significant enhancement in maximum available power gain ( Gma), maximum transducer power gain ( G MT), maximum unilateral power gain (MUG), maximum frequency of oscillation ( f MAX) and stern stability factor ( K) have also been observed for GME-TRC MOSFET due to reduced short channel effects (SCEs) and enhanced current driving capabilities. Further, the experimental data for grooved gate MOSFET has also been verified with the simulated data and a good agreement between their results is obtained.

Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization

The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated in this paper. First, the main variation sources in SNWTs are overviewed, with the detailed discussion on the specific sources of NW cross-sectional shape variation, random dopant fluctuation in NW source/drain extension regions and NW line-edge roughness (LER). Then, following the measurement-modeling approach, via calibrated statistical simulation that is based on the modified analytical model for GAA SNWTs with corrections of quantum effects and quasi-ballistic transport, the variability sources in SNWTs are experimentally extracted from the measured devices with 10-nm-diameter NW channels and TiN metal gate. The results indicate that NW radius variation and metal-gate work function variation dominate both the threshold voltage and on-current variations due to the ultrascaled dimensions and strong quantum effects of GAA NW structure. The NW LER also contributes, but relatively less, to the threshold voltage variation.

Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs

A simulation methodology for ultra-scaled InAs quantum well field effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp3d5s* tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass based ballistic quantum transport model is employed to simulate three terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I-V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage magnitude of the QWFETs, (i) the geometry of the gate contact (curved or square) and (ii) the gate metal work function. In addition to pushing the threshold voltage towards an enhancement mode operation, a higher gate metal work function can help suppress the gate leakage and allow for much aggressive insulator scaling.

Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function

Fully depleted (FD) Silicon on Insulator (SOI) metal oxide Field Effect Transistor (MOSFET) Is the Leading Contender for Sun 65nm Regime. This paper presents a study of effects of work functions of metal gate on the performance of FD-SOI MOSFET. Sentaurus TCAD simulation tool is used to investigate the effect of work function of gates ont he performance FDSOI MOSFET. Specific channel length of the device that had been concentrated is 25nm. From simulation we observed that by changing the work function of the metal gates of FD-SOI MOSFET we can change the threshold voltage. Hence by using this technique we can set the appropriate threshold voltage of FD-SOI MOSFET at same voltage and we can decrease the leakage current, gate tunneling current and short channel effects and increase drive current.

Ni-FUSI metal gate work function modulation technology

Through fabricating Ni-FUSI metal gate capacitors and analyzing their C-V and Vfb-EOT characteristics, it is found that Ga or Yb has more favorable modulation ability than conventional dopants. The work function of Ni-FUSI metal gate is modulated close to the top of valince band and the bottom of conduction band, which meets the requirement of high performance CMOS devices. The high modulation abilities of Ga and Yb are explained by dipole theory. Moreover, it is found that the capacitance value of Ni-FUSI metal gate capacitor increases after incorporating Ga or Yb into Ni-FUSI metal gate, but the gate leakage current decreases. And the detailed explanation for the above phenomena is also included in this article by analyzing C-V and gate leakage current characteristics.

Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

Control of Gate Metal Effective Work Functions and Interface Layer Thickness by Designing Interface Thermodynamics Based on Heteroatom Incorporation into High-k HfO2 Gate Dielectrics

We have proposed a new approach for controlling both gate metal effective work functions and interface layer thickness at the same time based on the incorporation of hetero atoms into HfO2 gate dielectrics. We investigated C atom incorporation into HfO2 by the first principles calculations. The results indicate that additional C atoms in HfO2 can reduce an interfacial SiO2 layer, which also causes modification of a gate metal effective work function. Redesigning interface thermodynamics by incorporating hetero atoms can be a crucial recipe for controlling both gate metal work functions and thickness of interfacial SiO2 layers in high-k gate stacks

(Invited) Issues on Interfacial Oxide Layer (IL) in EOT Scaling of High-k/Metal Gate CMOS for 22nm Technology Node and Beyond

According to the International Technology Roadmap for Semiconductors (ITRS), scaling to the 22 nm technology generation and beyond is facing significant challenges related to the timely implementation of high-k/metal gate stacks, including appropriate tuning of the metal gate work function, adequate channel mobility, and reliability. Scaling equivalent oxide thickness (EOT) becomes more challenging as it will reflect interfacial oxide layer (IL) scaling causing some issues such as mobility degradation and difficulty in achieving PMOSFET Vt target. This paper discusses issues on IL in the scaling the EOT of high-k/metal gates tacks.

Investigation of gate-all-around silicon nanowire transistors for ultimately scaled CMOS technology from top-down approach

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the key issues regarding SNWTs from the top-down approach including process integration, carrier transport, and fluctuation and variability in these unique one-dimensional stronglyconfined nanowire devices. A new process integration scheme for SNWTs is discussed, which features a fully-Si-bulk substrate, an epi-free process, a self-aligned structure and a large source/drain fan-out. The physical characteristics of the fabricated devices with 10-nm-diameter nanowires are further investigated. The carrier transport performance in SNWTs is experimentally estimated, with a modified extraction methodology which takes into account the impact of temperature dependence of parasitic source resistance. SNWTs with sub-40-nm gate lengths exhibit high ballistic efficiency at room temperature, indicating great potential for SNWTs as an alternative device structure for near-ballistic transport. For heat transfer in SNWTs, the self-heating effect is also characterized. However, due to the one-dimensional (1-D) nature of nanowires and increased phonon-boundary scattering in the GAA structure, the self-heating effect in SNWTs based on the bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus, special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally studied in detail. The results of extracted variation sources indicate that, with suppressed random dopant fluctuations in the intrinsic channel, variations in radius and metal-gate work function of SNWTs dominate both the threshold voltage and on-current fluctuations. Comparing with conventional planar MOS devices, SNWT based SRAM cells exhibit better stability due to the superior electrostatic control in SNWTs.

Tunable Work-Function Engineering of TiC–TiN Compound by Atomic Layer Deposition for Metal Gate Applications

In this paper, we present the impact of the atomic layer deposition of carbon-containing TiN films (TiC–TiN) on the effective work function of metal-oxide-semiconductor devices. By adjusting the deposition temperature of TiC–TiN, the carbon content, which is dependent on the deposition mode, could be altered. Hence, the work function of TiC–TiN as a metal gate material could be tuned. The results revealed that the bonding concentration of Ti–C increases at higher deposition temperatures, whereas the work function of the TiC–TiN metal gate decreases from 5.0 to 4.6 eV. A high work function (5.0 eV) metal gate is suitable for a p-field effect transistor (FET) application and the midgap work function (4.6 eV) is suitable for a fully depleted silicon-on-insulator FET.

Measurement of Dipoles/Roll-Off /Work Functions by Coupling CV and IPE and Study of Their Dependence on Fabrication Process

We study the effective metal gate work function (WF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Meff</sub> ) of different metal/high-κ gate stacks. Both capacitance versus voltage measurement and internal photo emission measurement were used, leading to a better understanding of the WF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Meff</sub> variations. We demonstrate that these variations are related to two main process dependent parameters, a voltage drop at the high- κ/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface and the metal work function. These two parameters are studied for various process conditions.

High work function metal gate and reliability improvement for MOS device by integration of TiN/MoN and HfAlO dielectric

Electrical characteristics and thermal stability of MOS devices with MoN/TiN metal stacks and various gate dielectrics were studied in this work. High work function (5.0 eV) gate is achieved by integrating MoN/TiN stack with HfAlO dielectric. The gate stack structures can enhance the thermal stability and reduce the interaction between the metal gate and the dielectric. The Ti diffusion in the dielectric can be suppressed by AlN in HfAlO. Reliability characteristics, in terms of stress-induced leakage current and stress-induced V fb shift, are improved for metal gate stack on HfAlO high- k dielectric in comparison with that on SiO 2. The work function of metal gate also can be turned by different Al contents in high- k dielectrics and metal gate stacks (4.88–5.0 eV).

Variable Interface Dipoles of Metallated Porphyrin Self-Assembled Monolayers for Metal-Gate Work Function Tuning in Advanced CMOS Technologies

This paper presents a technique for continuous tuning of the metal-gate work function (?metal) using self-assembled monolayer (SAM) of metallated porphyrins. Porphyrin SAM was prepared on SiO2 followed by Al evaporation to form MOS capacitors (MOSCAPs). The variation in the dipole moment achieved by changing the central metal ion (Zn, Cu, Ni, and Co) in metallated porphyrins has been shown as a way to modify the gate work function. Thermal gravimetric analysis (TGA) on Zn-porphyrin shows that the molecule is stable upto 450°C. Temperature stability experiments on MOSCAPs show that the above method can be effectively implemented in advanced CMOS technologies involving the gate-last process.