Metal Gate Work Function Research Articles

Performance Investigation of Pentacene Based Organic Double Gate Field Effect Transistor and its Application as an Ultrasensitive Biosensor

In this paper, the electrical performance of double gate organic field effect transistor (DG-OFET) are thoroughly investigated and feasibility of the device as an efficient biosensor is comprehensively assessed. The introduced device provides better gate control over the channel, yielding better charge injection properties from source to channel and providing higher on-state current in comparison with single gate devices. The susceptibility of fundamental electrical parameters with respect to the variation of design parameters is thoroughly calculated. In particular, standard deviation and average value of main electrical parameters signify that metal gate workfunction, channel thickness and gate oxide thickness are fundamental design measures that may modify the device efficiency. The insensitivity of off-state current to the change of channel length and drain bias confirms feasibility of the device in nanoscale regime. Next, a nano cavity is embedded in the gate insulator region for accumulation of biomolecules. The immobilization of molecules with different dielectric constants in the gate insulator hollow alters the gate capacitance and results in the drain current deviation with respect to the air- filled cavity condition. It is shown that by the occupancy of whole volume of the nanogap, a maximum range of on-state current variation can be achieved.

Analytical Modeling of Short-Channel Fully-Depleted Triple Work Function Metal Gate (TWFMG) SOI MESFET

In this paper, a new structure: triple work function metal gate SOI MESFET, intended for integration into the deep-submicron CMOS technology, is proposed. The gate of the device consists of three different materials which are laterally merged into one. The difference in the work function of dissimilar gate materials introduces two step changes in the profile of channel potentials which screens the threshold-defining region of the channel from the impact of drain potential. Therefore, the effects associated with DIBL are significantly alleviated. On the basis of exact solution of the Poisson equation in the channel region, an analytical subthreshold model for the device is developed. Using the analytical data, the device has been characterized and compared with conventional device in terms of potential function, DIBL, threshold voltage roll-off, and subthreshold swing. The TCAD simulator ATLAS from Silvaco has been used to validate the analytical results. The feasibility of device fabrication is also demonstrated.

Dipole-induced modulation of effective work function of metal gate in junctionless FETs

In this work, a metal gate with a high effective work function (Weff) that is suitable for junctionless field-effect transistors (JLFETs) has been fabricated. Weff is modulated by inserting an Al interfacial layer with different thicknesses between the HfO2 dielectric layer and the Pt gate metal. Transmission electron microscopy together with capacitance–voltage (C–V) measurement is used to investigate the underlying mechanism of this phenomenon. It is suggested that the oxygen scavenging from HfO2 by the Al layer leads to the formation of interface dipoles, which effectively modulate Weff. By varying the Al layer thickness, it is found that Weff first increases and then decreases as the Al thickness increases above ∼2.5 nm, and the largest increase in Weff is about 0.56 eV. Based on these results, our work provides a useful method using interface dipoles to adjust Weff to the desired value for JLFETs, which is otherwise difficult to achieve using a single metal.

Electric Field and Surface Potential Analytical Modeling of Novel Double Gate Triple Material PiN Tunneling Graphene Nano Ribbon FET (DG-TM-PiN-TGNFET)

A new two-dimensional analytical model for surface potential, electric field, band-to-band (B2B) tunneling rate and transconductance of a novel double gate triple material PiN tunneling graphene nano-ribbon field effect transistor (DG-TM-PiN-TGNFET) is proposed in this work. This physics-based analytical model incorporates the effects of different gate metal work functions, gate and drain voltages, body thickness and insulator thickness. In this model, the gate region has been divided into three segments where three different metals with different metal work functions are used. The purpose of using different work functions is to restrict the drain-source reverse tunneling. Low band-gap material viz. graphene is used as nano-ribbon to tune the energy band-gap as less as possible. This expands the tunneling window, where band-to-band tunneling (B2B) is considered to take place largely across source-channel region. This practice not only boost the ON current but also control the leakage current (Ambipolarity). It further improves the ON/OFF switching ratio for making this model suitable as fast switching device. Two-dimensional non-linear Poisson’s equation is derived to model electrostatic potential and electric field along the channel. Analytical results are compared with simulated DG-TM-PiN-SiTFET and proposed DG-TM-PiN-TGNFET for validation of work. Silvaco T-CAD numerical device simulator is used for simulation purpose.

Two-dimensional analytical modeling of the surface potential and drain current of a double-gate vertical t-shaped tunnel field-effect transistor

We present a two-dimensional (2-D) analytical modeling of the surface potential of a double-gate vertical t-shaped tunnel field-effect transistor (TFET), considering the inherit dual modulation effect in such devices. This effect explains the control of the surface potential by both bias voltages, which are used to calculate the tunneling depletion width at the source and drain junctions. A model of the tunneling current in the device is derived based on the surface-potential model. The parabolic approximation is used to solve the 2-D Poisson equation with appropriate boundary conditions. The dependence of the surface potential profile on different parameters is analyzed by varying the gate–source potential, drain–source potential, gate oxide dielectric constant, gate metal work function, and different materials used. Finally, expressions for the surface potential of the channel along with the tunneling current are obtained, accurately capturing their variation with the gate and drain biases. The proposed method is verified by the agreement between its analytical results and technology computer-aided design (TCAD) simulation results.

Modeling and simulation analysis of SiGe heterojunction Double Gate Vertical t-shaped tunnel FET

This paper deals with a new 2-D analytical surface potential model for heterojunction SiGe Double Gate Vertical t-shaped Tunnel Field Effect transistor and contemplate the inherit property of TFET that is dual modulation effect. This influence explains the control on the surface potential of the both biasing voltages at source and drain junctions that are used to measure the tunneling depletion widths. Therefore, the tunneling current uses the surface potential model as the basic for driving current model for the device. Parabolic approximation techniques are used to solve the equation of 2-D Poisson with the appropriate boundary conditions. We analyze the dependence of the surface potential profile on different parameters by varying the molefraction variation of SiGe material, gate source potential, drain source potential, gate oxide dielectric constant, gate oxide thickness, gate metal work function and different material used. Ultimately, we have the expression for the channel's surface potential along with tunneling current which have the accurate variation with the gate and drain biases. Efficiency of the proposed method has been confirmed by demonstrating the analytical results agreement with the TCAD simulation results.

Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors

In this paper, a two dimensional analytical model of the threshold voltage for HGD TFET structure has been proposed. We have also presented the analytical models for the tunneling width and the channel potential. The potential model is used to develop the physics based model of threshold voltage by exploring the transition between linear to exponential dependence of drain current on the gate bias. The proposed model depends on the drain voltage, gate dielectric near the source and drain, silicon film thickness, work function of gate metal and oxide thickness. The accuracy of the proposed model is verified by simulation results of 2-D ATLAS simulator. Due to the reduction of the equivalent oxide thickness, the coupling between the gate and the channel junction enhances which results in lower threshold voltage. Tunneling width becomes narrower at a given gate voltage for the optimum channel concentration of 1016 /cm3. The higher concentration in the source (Ns) causes a steep bending in the conduction and valence bands compared to the lower concentration which results in smaller tunneling width at the source-channel interface.

Ultrasensitive Multilayer MoS2‐Based Photodetector with Permanently Grounded Gate Effect

Abstract2D materials, specifically MoS2 semiconductors, have received tremendous attention for photo‐sensing applications due to their tunable bandgap and low noise levels. A unique photodetector using multilayer MoS2 as the semiconductor channel, in which the gate electrode of the device is permanently connected to the grounded source electrode to introduce rectification, is reported. The proposed grounded‐gate photodiode exhibits high photoresponsivity of 1.031 A W−1, excellent photodetectivity (>6 × 1010 jones), and highly stable rise/fall time response (100–200 ms) under illumination of visible light (at the wavelengths of 405, 532, and 638 nm). Numerical device simulations using quantum transport methods and photoconductive effects are used to explain the device operation. It is also suggested that the gate metal work function can be carefully chosen to increase the sensitivity of the grounded‐gate photodetector by suppressing the dark current. The grounded‐gate device proposed, owing to the properties of rectifying behavior, low contact resistance, consistent photoresponsivity, and linear sensitivity, provides a new platform for next‐generation applications in the field of electronics and optoelectronics.

Analysis on DC and RF/Analog Performance in Multifin-FinFET for Wide Variation in Work Function of Metal Gate

It is well established that increase in number of fins improves the RF/Analog performances of FinFET. In this paper, the effect of work function (ɸM) of metal gate on transfer characteristics, on current (Ion), off current (Ioff), threshold voltage (VT), and subthreshold swing (SS) are reported in Multifin-FinFET. It is seen that both the current ratio (Ion/Ioff) and SS improves as ɸM changes from 4.4 to 4.7 eV. Impact of ɸM on RF/Analog parameters like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd), gate capacitance (Cgg), and cut-off frequency (ft) are investigated for Multifin-FinFET. Analysis reveals that intrinsic gain and cut off frequency improves with increase in ɸM of metal gate.

A 2-D Analytical Modeling of Dual Work Function Metal Gate MOSFET Using High-K Gate Dielectric with Enhanced RF/Analog Performance for Low Power Applications

A 2-dimensional electrostatic potential modeling of fully depleted channel, with high-k based dual work function double gate (DWFDG) MOSFET, has been developed in this paper. The expression for electrostatic potential of DMDG has been developed using 2-D Poisson’s equation with appropriate device boundary conditions along the device gate length. The high-k based DWFDG MOSFET shows a significant decrease in short channel effects (SCEs), by using step in electrostatic potential near the interface of gate materials (M1) and (M2). The impact of device limitations such as electrostatic potential with oxide thickness, channel thickness, different gate bias and drain bias on the capability of the device has been examined using novel analytical model. The validation of the analytical modeling results are verified with numerical simulation by using 2-dimentional Sentaurus TCAD device simulator. In addition, the simulation has been performed for finding analog performances of the proposed device as compared with conventional device. The significant improvement in drain current, Ion/Ioff ratio, output conductance and gm/Ids have been observed. Hence, the simulation results shows that the proposed device is best suitable for faster switching and low power applications.

Impact of Structural Aspect, Metal Gate and Channel Material on UTB-SOI-MOSFET

Ultra Thin Body Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (UTB-SOI-MOSFETs) provide better immunity to Short Channel Effects (SCEs). But the behaviour changes at miniaturization and still the many unexplored effects need to be analysied. Here in this paper, Drain Induced Barrier Lowering (DIBL) and sub-threshold Slope (SS) variation of a n-channel UTB-SOI-MOSFET have been analyzed by changing the device structural aspects like gate length (LG), BOX thickness (tBOX) and Silicon film thickness (tSi). Also, the effect of intrinsic parameters as metal gate work function and channel material variation on DIBL and sub-threshold Slope (SS) variation has been analyzed.

3D Investigation of 8-nm Tapered n-FinFET Model

The miniaturization has become a key word for advanced integrated circuits over the last few years. It is within this context that the fin field effect transistor (FinFET) has appeared as a suitable technology to enable in every single chip to contain more million transistors. This paper proposes a numerical investigation of the influence of the gate length, drain/source doping concentrations, and gate work function on the output properties of 3D tapered FinFET technology by using Silvaco TCAD tools. The simulation results show that decreasing the gate length from 14 nm to 6 nm, the leakage current enhances dramatically and increasing the metal gate work function from 5.33 eV to 5.70 eV has affected transistor response time and the on-current, but in parallel, the leakage current increase affecting the transistor efficiency. The subthreshold slope (SS) and transconductance (gm) are quite constant for all work function levels. This variation leads to determine the optimal metal gate work function of about 4.50 eV. The paper reports recent findings and some guidelines to achieve the following results: a threshold voltage (Vth) of 0.216 V, a subthreshold slope of 68.54 mV/dec, a transconductance of 315.7 μA/V, an on-current (Ion) of 103.75 μA, and an off-current (Ioff) of 2.51 nA with a fixed gate length (Lg) of 8 nm, a top fin-width (FWT) of 3 nm, a bottom fin-width (FWB) of 6 nm, and a fin-height (FH) of 50 nm, which are close to those reported in other research studies.

Analysis of Deep Level and Oxide Interface Defects Using 100V HF Schottky Diodes and MOS CV for Silicon and 4H SiC HV MOSFETs, Advanced Power Electronics, and RF ASIC

AbstractIn this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.

Design Considerations and Capacitance Dependent Parametric Assessment of Gate Metal Engineered SiNW MOSFET for ULSI Switching Applications

This work investigates design consideration of Gate Electrode Workfunction Engineered (GEWE) silicon nanowire MOSFET at room temperature. It is perceived from the results that the parasitic capacitances are higher in the deep inversion region, however; the coupling of parasitic capacitance is weak in GEWE-SiNW due to lower gate metal workfunction at the drain end. Moreover, the influence of drain voltage on Cgs is very less owing to constant depletion charges at the source side which results in almost constant value of Cgs with the change in Vds. With tuning of channel length (Lg) and oxide thickness (tox), the effect of capacitances in GEWE-SiNW further reduces significantly due to quantization effect at such scaled dimensions. Furthermore, Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) have also been calculated with an aim to analyze the device DC and switching performance as they are directly or indirectly linked with parasitic capacitance. Calibrated 3D simulations validate that the GEWE-SiNW MOSFET exhibit 2.57, 34.5 and 2.75 times improvement in TFP, EDP and GBP respectively in comparison to SiNW in the linear region.

Impact of band to band Tunneling on Transient performance of Dual Gate Tunnel Field Effect Transistor (TFET)

Tunnel Field Effect Transistor (TFET) is gated reverse biased P-I-N diode structured semiconductor device and can be considered as a reliable low power device. TCAD (Sentaurus 2D) simulations for various Gate metal work function (4.1-4.3 eV) shows that its ON-current (ION) arises from quantum mechanical band-to-band tunneling (B2BT) and observed that threshold Voltage (VT) for TFET decreases with increase in Gate metal work function. The thermionic emission of electrons in MOSFET limits the sub-threshold swing (SS) by 60 mV/dec whereas TFET has potential for low SS ie. SS<60 mV/dec. TCAD Simulations confirmed that that the Gate – Drain capacitance (Cgd) strongly follows the Gate capacitance (Cgg) all over the voltage range (0-0.9V) which increases the miller capacitance for TFET. It is investigated that for TFET, the injection of carriers into the channel is through B2BT which effectively couples the Gate charge to the Drain. A look up table based Verilog-A model is generated for TFET and used to simulate the static and dynamic behavior of TFET based digital circuit in Cadence spectre. Miller effect causes the peak voltage overshoots are noticed at the drain side during transient responses and can be responsible for dynamic power loss and high turn ON/OFF delay

Performance optimization of a nanoscale GaSb P-channel electron-hole bilayer tunnel field effect transistor using metal gate workfunction engineering

In this paper, the electrical characteristics of a double gate P-channel GaSb Electron-Hole Bilayer Tunnel Field Effect Transistor (EHBTFET) is comprehensively investigated and impact of main design parameters on the performance of the device is thoroughly assessed. The corresponding low carrier effective mass of GaSb provides high probability of tunneling current that eventually exhibits an improvement in the on-state current and subthreshold swing (SS). The results reveal that unlike the conventional tunnel field effect transistor (TFET) in which band to band tunneling current occurs horizontally from source to channel, the tunneling junction in EHBTFET is electrically created in the intrinsic channel in the entire region of the gate overlap length along the vertical direction. Due to the expanding of the tunneling area, the on-state current of EHBTEFT is increased five order of magnitude in comparison with lateral TFET and subthreshold swing of SS = 2 mV dec−1 with on/off current ratio of 2.5 × 1011 is achieved. The top and bottom gate workfunction are critical design parameters that fundamentally affect the tunneling rate. The 2D variation matrix of threshold voltage and on-state current are calculated as a function of top and bottom gate workfunction for optimizing the device performance. In addition, a comprehensive sensitivity analysis via calculating standard deviation and mean value of main electrical parameters are assessed to evaluate the susceptibility of device performance with respect to the variation of design parameters. The main feature of this device is the insensitivity of the tunneling rate to the source doping density that solves the problem of low solubility of dopants in III-V materials. Moreover, subthreshold swing and off-state current and are not affected by the gate length scaling, facilitating the employment of this device in nanoscale regime. The results in this paper pave the way for designing low power steep-slope logic circuits.

Realizing a Planar 4H-SiC Junctionless FET for Sub-10-nm Regime Using P+ Pocket

In this paper, using calibrated device simulations, we propose the use of a P± pocket at channel-drain and channel-source interfaces in 4H-SiC junctionless FET (4H-SiC p-JLFET) to achieve efficient volume depletion in the sub-10-nm regime; thus relaxing the need of channel thickness scaling or the use of complex device architectures. The P± pocket improves the OFF-state current (IOFF) by ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> , while slightly degrading the ON-state current (ION) and subthreshold slope (SS) for a 7-nm channel length device. This large gain in IOFF presents the possibility of realizing multiple threshold voltage (VTH) devices by tuning the metal-gate work function, which helps in creating optimized designs in terms of area, power, leakage, and performance, which is not possible in Si JLFETs, due to their need of high metal-gate work functions to achieve volume depletion even at larger channel lengths. The 4H-SiC p-JLFET gives ~1pA/μm IOFF even at an elevated temperature of 600 K. We also discuss the scaling of the SiC p-JLFETs for 7-and 5-nm channel length.

Combined nanoscale KPFM characterization and device simulation for the evaluation of the MOSFET variability related to metal gate workfunction fluctuations

In this work, a more realistic approximation based on 2D nanoscale experimental data obtained on a metal layer is presented to investigate the impact of the metal gate polycrystallinity on the MOSFET variability. The nanoscale data (obtained with a Kelvin Probe Force Microscope, KPFM) were introduced in a device simulator to analyze the effect of a TiN metal gate work functions (WF) fluctuations on the MOSFET electrical characteristics. The results demonstrate that the device characteristics are affected not only by the WF fluctuations, but also their spatial distribution, which is specially relevant in very small devices. The effect on these characteristics of the spatial distribution on the gate area of such fluctuations is also evaluated.

Two-dimensional model for double-gate LDMOSFET devices

A two-dimensional compact model of a double-gate LDMOSFET is presented in this work. The impact of controlling the drift region resistance by controlling the bias and/or gate metal work function of a separately added second gate of the LDMOSFET electrostatics is investigated while trading off the breakdown behavior in terms of the surface longitudinal field. Compact models for the surface potential and surface longitudinal electric field based on the 2D solution of Poisson’s equation are introduced. The effects of the second gate on the threshold voltage roll-off are studied in this work. The introduced models are verified to have good agreement with the numerical simulation results. The results of the study show that the introduced structure with its newly introduced separately biased second gate provides some degree of freedom for controlling the ON-resistance and threshold voltage. A Verilog-A SPICE model for the drift region based on the introduced models is implemented to be compatible with circuit simulators along with standard MOSFET devices. Using this Verilog-A implementation, it is shown that the effective drift resistance is enhanced by approximately 14%, representing a 40% increase in the second gate bias at the same drift doping level. Moreover, increasing the drift doping slightly enhances the controllability of the effective drift resistance by 0.7%, representing a 40% increase in the second gate bias. By varying the second gate bias for the different drift region lengths from 1 to 2 μm, a 0.8% decrease in the controllability of the effective drift resistance versus the second gate bias is obtained. Also, the breakdown voltage is increased by about 6%, depending on drift doping level, as increasing the second gate voltage by about 40% from its nominal value.

Novel Exploration of Flat-Band Voltage Manipulation by NPT for Advanced High-k/Metal-Gate CMOS Technology

Threshold voltage (VT) modulation is crucial for high performance (HP) and low power (LP) applications in the state-of-the-art FinFET and NanowireFET devices with gate-last HKMG integration scheme. Conventional metal-gate work function modulation normally requires a complicated film stack structure and a precise film thickness control in RMG (Replaced Metal Gate) process. As the physical gate length of RMG scaling down to below 14nm for sub-7nm technology node, the gap filling volume becomes rigorous and the VT tuning capability and turns inadequate for CMOS IC applications. This work presents a novel exploration of flat-band voltage (VFB) manipulation scheme with the nitrogen plasma treatment (NPT) in the high-k/metal-gate (HKMG) Metal-Oxide-Semiconductor Capacitor (MOSCAP) for the shrinking scaling of the further CMOS fabrication technology. HKMG formation is performed via ALD (Atomic Layer Deposition) and CVD (Chemical Vapor Deposition). The gate stacks of fabricated P- and N-MOSCAPs are ALD-HfO2(High-k layer, HK)/ALD-TiN(Capping layer)/ALD-TaN(Etch-stop layer, ESL)/CVD-TiN(Work-function layer, WFM)/ALD-W(Contacted metal) and ALD-HfO2(High-k layer, HK)/ALD-TiN(Capping layer)/ALD-TiAlC(Work-function layer, WFM)/ALD-TiN(Barrier layer)/ALD-W(Contacted metal), respectively. The critical NPT process is developed in chamber of EnduraTM (Applied Materials, Inc) and compatible to the mainstream gate-last HKMG technology. NPT process is applied in the first ALD-TiN capping layer both for P- and N-MOSCAPs. The developed NPT process on the first ALD-TiN capping layer demonstrates significant VFB modulation capability and causes a controllable effective work function of metal gate: 1) shifting to band center with increasing of the radio frequency powers both for P-/N-MOSCAPs; 2) shifting to opposite directions (P- to band edge, N- to band center) with reduced nitrogen flow ratio for P-/N-MOSCAPs; 3) shifting from -220mV to +60mV and from +130mV to +420mV for P-/N-MOSCAPs, respectively. Compared to the samples without NPT, the gate leakage current of both P- and N-MOSCAPs are improved with the NPT process. Based on the different gate stacks of P-/N-MOSCAPs and plasma effect, one unique physical model including N-vacancy/Al-trap effect is successfully proposed to illustrate the complicated shift behaviors both for HKMG P-/N-MOSCAPs. VFB shift for P-MOSCAP is mostly determined by N-vacancies, for the same layer of first capping layer(TiN) and work-function layer(TiN). The VFB shift for N-MOSCAP needs to consider both N-vacancies and Al-traps effect, for the difference between first capping layer(TiN) and the upper work-function layer(TiAlC). In conclusion, the technology of NPT in the first ALD-TiN capping layer of HKMG MOSCAPs for gate work function modulations is systematically investigated. Significant VFB shift values, such as -220mV/+130mV with different RF powers and +60mV/+420mV with different nitrogen flow ratios are achieved for P-/N-MOSCAPs, respectively. One simple theoretical model by employing the function of N-vacancy in ALD-TiN capping layer with the corresponding Al-trap effect by different WFM atoms in metal-gate is presented, which gives a unique physical explanation to the complex VFB manipulation behaviors with different device types and process conditions. The results demonstrate NPT process is one of the most promising technologies for the VT manipulation in future scaling CMOS technology nodes with less process cost. Figure 1