Gate Material Engineering Research Articles

Linearity and intermodulation distortion analysis of single and dual metal gate junctionless transistor

Linearity and intermodulation distortion are very crucial parameters for RFICs design. Therefore, in this work, a detailed comparative analysis on linearity and intermodulation distortion of single metal (SMG) and double metal (DMG) double gate junction less transistor (JLT) is done using TCAD silvaco suite. Furthermore, the effects of temperature fluctuation, gate length variation, and gate material engineering on the linearity performance of both devices are also studied. A few significant figures of merit, including Voltage Intercept Point 2 (VIP2), Voltage Intercept Point 3 (VIP3), Third Order Intercept Power (IIP3), 1 dB Compression Point (P1dB), Third Order Intermodulation Distortion (IMD3), and the transconductance derivative parameters First Order Transconductance (gm1), Second Order Transconductance (gm2), and Third Order Transconductance (gm3) are used to assess the device linearity and intermodulation distortion of SMG and DMG JLT's. The findings show that higher VIP2, VIP3, IIP3, 1-dB compression point and lower gm3, IMD3 values are obtained for the SMG JLT device when compared to its counterpart DMG JLT. SMG JLT, which assures strong linearity and low distortion.

Effect of Temperature, Doping and Gate Material Engineering on Tri-Gate SOI nFinFET Performance Through TCAD Simulation

Effect of Temperature, Doping and Gate Material Engineering on Tri-Gate SOI nFinFET Performance Through TCAD Simulation

Qualitative Analysis of DG-TFET Structures with Gate Material Engineering

The paper largely focuses on enhancing device parameters of a Double Gate Tunnel Field Effect Transistor structure such as ON current, OFF Current,transconductance and ratio of ON current to OFF current (ION / IOFF) using hetero dielectric gate material. The paper presents three state of art of dual gate TFET i.e., Conventional Double Gate TFET (CDGTFET), horizontally placed Dual Material Double Gate TFET (HDMDGTFET), vertically placed Dual Material Double Gate TFET (VDMDGTFET). The dual material dielectric combinations used in the structures are (SiO2-TiO2), (HfO2-TiO2) and (SiO2-SiC). The Structures are being modeled using Silvaco Atlas tool. Simulations of these structures are carried out and various electrical parameters have been obtained. The results obtained from simulation of these structures are being presented and discussed in this paper. Comparison of the three structures is carried out and resulted in the reduction of ON Current and OFF Current is observed.

Performance Analysis and Comparison of Different High-K Materials Used as Gate Dielectrics in DH-TMSG MOSFET

Abstract: To overcome SCEs and provide better packing density and performance a device called Double Halo Triple Material Surround Gate MOSFET is introduced. The device is designed by the combination of gate engineering and channel engineering. The device uses a surround gate MOSFET with triple material gate employing gate material engineering which improves the gate transport efficiency by modifying electric field pattern and surface potential along channel, resulting in higher carrier transport efficiency and SCEs. To extend the use of CMOS technology beyond 14 nm node technology, new device materials are required that can enhance the performance of MOSFETs. The use of high-k materials in double gate (DG) MOSFET can triumph over the problem of power dissipation and leakage current. The further mitigation in device dimension becomes a challenging task due to the existence of unavoidable short channel effects. The introduction of gate stack and channel engineering in MOSFET devices open a new window for future generation devices. The gate dielectric materials have played a significant role in the design of novel and high performances at nanoscale of electrical devices. It can be observed that when approaching a higher value of dielectric constant, the on current increases while the subthreshold slope (SS) threshold voltage (Vth) and leakaga current reduced. The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large.

Analytical modelling and sensitivity analysis of Gallium Nitride-Gate Material and, dielectric engineered- Schottky nano-wire fet(GaN-GME-DE-SNW-fet) based label-free biosensor

An analytical model of nanogap embedded Gallium Nitride Gate- Material and Dielectric Engineered- Schottky Nano-Wire Field Effect Transistor (GaN-GME-DE-SNW-FET) for implementation as a label-free biosensor is introduced. An expression for the surface potential is attained by resolving the 1-D Poisson equation and 2-D Laplace equation utilizing a superposition method. A Model for the threshold voltage is also developed to analyze the sensitivity of the biosensor. The projected model also contains the repercussion of barrier height dropping at the metal-semiconductor intersection along with Dielectric Engineering (DE) using high-k (HfO2) material and Gate Material Engineering (GME) using metal m1with workfunctionφm1and m2with workfunctionφm2. The sensitivity of biosensor's has been studied for diverse dielectric constant and charge densities immobilized within the nanogap cavity. A comparative study has also been done between Gallium nitride-based (GaN- GME-DE-SNW-FET) and Silicon-based (Si-GME-DE-SNW-FET) Label-free biosensors. The developed analytical model is verified and validated using ATLAS- TCAD device simulations.

Investigation of Gate Material Engineering in Junctionless Transistor for Digital and Analog Applications

In this paper, we propose dual material gate with dual-k dielectric gate oxide double gate junctionless transistor ‘DMG-DK-JLT’ for significant enhancement of performance. We showed, using 2D simulation that the proposed DMG-DK-JLT exhibit: 1) suppressed gate induced drain leakage due to band to band tunneling in OFF state (VDS = 1 V, VGS = 0 V) by 5 orders. 2) Impressively high ION/IOFF ratio of ~108. 3) For VGS=VDS = 1 V, DMG-DK-JLT performs better over conventional double gate JLT on various digital and analog performance metrics such as transconductance (Gm, 64% improvement), early voltage (VEA, 107% improvement), intrinsic gain (GmRO, 294% improvement), unity gain cutoff frequency (fT, 48% improvement), output resistance (Ro, 139% improvement), and transconductance-to-drain current ratio (Gm/ID, 218% improvement at VGS = 0.2 V, VDS = 1 V). We also compared its performance on above metrics with other gate material engineered Junctionless transistors. Moreover, we also show these values are further improved several orders by adding high-k gate sidewall spacer to our proposed DMG-DK-JLT.

Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications

In this paper, gate-stacked gate-material-engineered junctionless nanotube MOSFET (GS GME JL NTMOSFET) was proposed for digital circuits. In GS configuration, hafnium-based high-k dielectrics (HfO2 and HfxTi1−xO2) were used in gate-stacked engineering (for inner as well as outer gate oxide). The performance of proposed device was compared with non-stacked GME JL NTMOSFET and analysed. GS GME JL NTMOSFET offered a significant reduction in leakage current (~ 10–16) and improvement in ION/IOFF ratio (~ 1011) as compared to non-stacked device. It was found that side spacer with suitable dielectric constant can be considered to improve the ION/IOFF ratio, SS, DIBL of the proposed device. Furthermore, the CMOS inverter circuit of purposed device was designed to investigate its digital performance. Therefore, GS GME JL NTMOSFET with adequate design parameters and dielectric material may be used in future digital applications.

Reduction of Drain Induced Barrier Lowering in DM‐HD‐NA GAAFET for RF Applications

In this research work, a dual-metal hetero-dielectric with nitride gate all around field effect transistor (DM-HD-NA GAAFET) has been proposed to address and mitigate an essential issue of drain induced barrier lowering and tunnelling leakage current. This device also provides better transconductance, output conductance, early voltage, and transforming growth factor so that it can also be used for radio-frequency (RF) applications. In this structure, silicon dioxide (SiO 2 ) is used at the source side while the silicon nitride (Si 3 N 4 ) is used at drain side to reduce tunnelling of charge. In DM-HD-NA GAAFET, gate material engineering (GME) technique is also being used in which higher work function metal is used at source side in order to accelerate charge carriers while lower work function metal is used at drain side so that it can increase ON-state current ( I ON ). The obtained results are compared with dual-metal hetero-dielectric with vacuum gate all around field effect transistor (DM-HD-VA GAAFET) to analyse its performance. In the proposed device structure, I ON increased by GME approach while I OFF decreased by hetero-dielectric method so it improves I ON / I OFF ratio for DM-HD-NA GAAFET compared to DM-HD-VA GAAFET device.

2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET

This paper reports a physics-based analytical model for the cylindrical-gate (CG) asymmetric halo doped graded-channel (GC) dual-material (DM) junctionless-accumulation-mode (JAM) MOSFETs by incorporating both the effects of gate material engineering and channel engineering on the device characteristics. Poisson’s equation has been solved using the superposition technique with appropriate boundary conditions. The minimum central potential concept has been used to derive the threshold voltage model. The drain and gate currents have been modeled by including the effects of gate induced drain leakage (GIDL) and gate leakage currents, respectively. The performance parameters of the proposed CG-GCDM JAM MOSFETs have been compared with those of the CG-DM and CG-GC JAM-MOSFETs to show that the proposed structure has enhanced reliability against short channel effects (SCEs), hot carrier effects (HCEs) and various leakage currents (GIDL and gate leakage) for various control-to-screen gate length ratios. The proposed modeled results have been validated by comparing them with numerical data obtained by using a 3D commercial TCAD simulator.

Examining the Electrical characteristic for Triple Material Double-Gate Silicon-On-Nothing (SON) MOSFETs with High Dielectric Oxide: A Comparative Study

Demand for devices with higher processing speed and lower power consumption increase exponentially every year. The device industry achieved these demands by the down-scaling device structures. As device size decreases, the physical parameters also decrease. This results in several critical issues. One such an issue is the decreasing of device threshold voltage. This decrease in threshold voltage is the result of decrease in control by the gate above the channel region and source/drain charge sharing. Silicon-on-nothing (SOI) and Silicon-on-insulator (SON) are among some structural solutions to tackle this issue. In this paper, studies on the effects of various physical parameters to the threshold voltage of a double-gate SON metal oxide semiconductor field-effect transistor (MOSFET) has been presented. The concept of high dielectric material on the oxide layer and gate material engineering is also incorporated. A comparison between SON and SOI is also carried out on the ATLAS simulator.

Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications

A simple continuous analytical model is developed for the drain current of unipolar junction dual material double gate MOSFET (UJDMDG). The model is based on electrostatic potentials obtained from the solution of Poisson’s equation using parabolic approximation method, surface potential, electric field, threshold voltage roll-off and drain current are explicitly modelled. Analytical results are verified and validated by comparing it with the result obtained from Silvaco TCAD ATLAS device simulator making it suitable for circuit design simulations. A comparative study of the short-channel effects (SCEs) for UJDMDG and unipolar junction single material double gate MOSFET (UJSMDG) structures has been carried out in order to show the efficacy of gate material engineering to suppress SCEs. Moreover, the variation of RF and analog figure of merits as a function of downscaled gate lengths has been reported. To exhibit the superiority in RF/analog performance of UJDMDG over UJSMDG MOSFETs, the analog/RF performance parameters has been studied and compared for SoC applications.

3D analytical modeling and electrical characteristics analysis of gate-engineered SiO2/HfO2-stacked tri-gate TFET

In this paper, we have incorporated the novel concept of gate material engineering in a three-dimensional tri-gate TFET structure with SiO2/HfO2-stacked gate oxide to reap the dual benefits of triple gate material and dielectric engineering in a single device. A detailed 3D analytical modeling of electrostatic potential distribution and electric field of the proposed structure is developed here solving 3D Poisson’s equation with suitable boundary conditions. Tunneling current is then extracted by integrating the band-to-band tunneling generation rate over the volume of the device. A comprehensive performance analysis of the present structure is analyzed in terms of potential profile, electric field and ON-current characteristics of the device by varying several parameters such as channel length, channel thickness, oxide thickness, applied gate and drain bias voltages. An overall performance comparison of the proposed structure with dual and single gate material equivalent tri-gate TFET structures with and without high-k gate stack is also demonstrated to explore the functional efficiency of the present structure. The results of the derived analytical model are compared with SILVACO ATLAS simulated data verifying the accuracy of our model in order to validate it for establishing the superiority of the structure.

Impact of gate material engineering on ED‐TFET for improving DC/analogue‐RF/linearity performances

To avoid the fabrication complexity and cost of nanoscale devices, a dual metal gate (DMG) in polarity controlled electrically doped tunnel field-effect transistor (ED-TFET) has been introduced first time for DC, analogue/radio frequency (RF) and linearity performance improvement. The formation of n+ drain and p+ source regions are done by applying polarity biases of PG-1 as 1.2 V and PG-2 as −1.2 V, respectively, over the silicon body in DMG-ED-TFET. Different analogue/RF and linearity performance metrics of DMG-ED-TFET are evaluated using ATLAS device simulator and compared with that of ED-TFET. The figure of merits (FOMs) studied in this work for DMG-ED-TFET are in terms of transconductance, gate-to-drain capacitance, gain bandwidth product, cut-off frequency and linearity parameters such as third-order transconductance coefficient ( g m 3 ), VIP3, IIP3 and IMD3. From the simulations, it is found that DMG-ED-TFET achieves significant improvement in these FOMs as compared to ED-TFET due to introduction of dual metal at gate electrode (gate workfunction engineering). The work has also optimised the proposed device to attain optimum analogue/RF and linearity performance.

Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics

In this work, we investigate for the first time dual material control gate junctionless tunnel-field effect transistor (DMCG-JLTFET) to improve the metrics in terms of DC, analog/RF parameters, and linearity performance. In this regard, we have considered N-type heavily doped silicon and formation of P+ source and intrinsic region beneath gate are performed by work-function engineering (dual material) concept with the deposition of metal electrodes over the silicon body, while, the drain region and the gap between source and channel remains with its original N+ doping. This forms the P+-N+-I-N+ gated structure similar to pocket doped TFET and prevents the device from random dopant fluctuations (RDFs). The gate electrode used to form the intrinsic region is partitioned into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with work-functions ϕM1, ϕM2 and ϕM3, respectively where (ϕM1 = ϕM3 < ϕM2). Appropriate work-functions for the gate electrodes (M1, M2 and M3) in DMCG-JLTFET are used to address the trade-off between the ambipolarity and RF/linearity parameters. It provides superior results in terms analog/RF and linearity performance as compared to other possible combinations.

Impact of gate engineering in enhancement mode n++GaN/InAlN/AlN/GaN HEMTs

This paper illustrate the effect of gate material engineering on the performance of enhancement mode n++GaN/InAlN/AlN/GaN high electron mobility transistors (HEMTs). A comparative analysis of key device parameters is discussed for the Triple Material Gate (TMG), Dual Material Gate (DMG) and the Single Material Gate (SMG) structure HEMTs by considering the same device dimensions. The simulation results shows that an significant improvement is noticed in the key analysis parameters such as drain current (Id), transconductance (gm), cut off frequency (fT), RF current gain, maximum cut off frequency (fmax) and RF power gain of the gate material engineered devices with respect to SMG normally off n++GaN/InAlN/AlN/GaN HEMTs. This improvement is due to the existence of the perceivable step in the surface potential along the channel which successfully screens the drain potential variation in the source side of the channel for the gate engineering devices. The analysis suggested that the proposed TMG and DMG engineered structure enhancement mode n++GaN/InAlN/AlN/GaN HEMTs can be considered as a potential device for future high speed, microwave and digital application.

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (Nit) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/− LC affects the device subthreshold performance. One-dimensional (1D) Poisson’s and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as Nit is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal–semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

Gate-Material-Engineered Junctionless Nanowire Transistor (JNT) With Vacuum Gate Dielectric for Enhanced Hot-Carrier Reliability

This paper reports the physics-based drain-current model for the gate-material-engineered vacuum junctionless nanowire transistor for improved hot-carrier reliability and analog/RF applications. The novel structure is based upon asymmetric gate oxide by combining the Al2O3 gate dielectric at the source side and the vacuum dielectric at the drain side, which significantly reduces the band-to-band tunneling effect, electric field, and drain-induced gate leakage. However, the vacuum dielectric enhances the immunity against the hot carriers' induced damage, but it has the deficiency of having a low drive current, transconductance, and therefore low $\mathbf{I}_{\mathbf{on}}/\mathbf{I}_{\mathbf{off}}$ current ratio. Therefore, gate material engineering is incorporated to make the device suitable for improved analog/RF applications. The analytical results are verified by the ATLAS TCAD device simulator.

Improved analog/RF performance of double gate junctionless MOSFET using both gate material engineering and drain/source extensions

In this paper, we propose a new Double Gate Junctionless (DGJ) MOSFET design based on both gate material engineering and drain/source extensions. Analytical models for the long channel device associated to the drain current, analog and radio-frequency (RF) performance parameters are developed incorporating the impact of dual-material gate engineering and two highly doped extension regions on the analog/RF performance of DGJ MOSFET. The transistor performance figures-of-merit (FoM), governing the analog/RF behavior, have also been analyzed. The analog/RF performance is compared between the proposed design and a conventional DGJ MOSFET of similar dimensions, where the proposed device shows excellent ability in improving the analog/RF performance and provides higher drain current and improved figures-of-merit as compared to the conventional DGJ MOSFET. The obtained results have been validated against the data obtained from TCAD software for a wide range of design parameters. Moreover, the developed analytical models are used as mono-objective function to optimize the device analog/RF performance using Genetic Algorithms (GAs). In comparison with the reported numerical data for Inversion-Mode (IM) DG MOSFET, our optimized performance metrics for JL device exhibit enhancement over the reported data for IM device at the same channel length.

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (gm), output conductance (gd), Early Voltage (VEA), Maximum Transducer Power Gain, cut-off frequency (fT), and Ion/Ioff ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable Ion of~31.8μA/μm and saturation transconductance gm of~68.2μS with improved third order derivative of transconductance gm3.

Performance Evaluation and Reliability Issues of Junctionless CSG MOSFET for RFIC Design

This paper investigates the reliability issues of junctionless cylindrical surrounding-gate (JL CSG) MOSFET by employing temperature variations, ranging from 200 K to 500 K, along with the influence of interface trap charges. Furthermore, the analog/RF performance evaluation and linearity distortion analysis due to the interface trap charges in terms of figure-of-merit metrics, i.e., drain current Ids; intrinsic gain (gm/gd) Ion/Ioff ; cutoff frequency fT; gain; gain transconductance frequency product; IMD3; VIP2; VIP3; IIP3; and higher order transconductance coefficients gm1, gm2, and gm3 of JL CSG MOSFET have been carried out. A direct comparative study in terms of performance degradation is made between gate material engineered (GME) and single-material gate (SMG) JL CSG MOSFET using ATLAS 3-D device simulator. Simulation results reveal that a GME JL transistor shows better immunity against the influence of interface trap charges and exhibits significant enhancement to maintain device linearization, as compared to an SMG JL CSG MOSFET, so that it can be used as a high-efficiency linear radio-frequency integrated-circuit design and wireless applications. Also from simulation study, degrading effects in JL CSG MOSFET are more pronounce at low temperature and subthreshold region. Apart from analog/RF performance, trap charges change the temperature sensitivity coefficient of the drain current and zero crossover point.