Abstract
In this paper, gate-stacked gate-material-engineered junctionless nanotube MOSFET (GS GME JL NTMOSFET) was proposed for digital circuits. In GS configuration, hafnium-based high-k dielectrics (HfO2 and HfxTi1−xO2) were used in gate-stacked engineering (for inner as well as outer gate oxide). The performance of proposed device was compared with non-stacked GME JL NTMOSFET and analysed. GS GME JL NTMOSFET offered a significant reduction in leakage current (~ 10–16) and improvement in ION/IOFF ratio (~ 1011) as compared to non-stacked device. It was found that side spacer with suitable dielectric constant can be considered to improve the ION/IOFF ratio, SS, DIBL of the proposed device. Furthermore, the CMOS inverter circuit of purposed device was designed to investigate its digital performance. Therefore, GS GME JL NTMOSFET with adequate design parameters and dielectric material may be used in future digital applications.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
